8043d5a964
The ability to specify alignment was recently added, and it's an important property which we should ensure is set as expected by Clang. (Especially before making further changes to Clang's code in this area.) But, because it's on the end of the lines, the existing tests all ignore it. Therefore, update all the tests to also verify the expected alignment for atomicrmw and cmpxchg. While I was in there, I also updated uses of 'load atomic' and 'store atomic', and added the memory ordering, where that was missing.
121 lines
4.0 KiB
C
121 lines
4.0 KiB
C
// RUN: %clang_cc1 %s -emit-llvm -o - -triple=i686-apple-darwin9 | FileCheck %s
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int atomic(void) {
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// non-sensical test for sync functions
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int old;
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int val = 1;
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char valc = 1;
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_Bool valb = 0;
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unsigned int uval = 1;
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int cmp = 0;
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int* ptrval;
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old = __sync_fetch_and_add(&val, 1);
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// CHECK: atomicrmw add i32* %val, i32 1 seq_cst, align 4
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old = __sync_fetch_and_sub(&valc, 2);
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// CHECK: atomicrmw sub i8* %valc, i8 2 seq_cst, align 1
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old = __sync_fetch_and_min(&val, 3);
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// CHECK: atomicrmw min i32* %val, i32 3 seq_cst, align 4
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old = __sync_fetch_and_max(&val, 4);
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// CHECK: atomicrmw max i32* %val, i32 4 seq_cst, align 4
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old = __sync_fetch_and_umin(&uval, 5u);
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// CHECK: atomicrmw umin i32* %uval, i32 5 seq_cst, align 4
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old = __sync_fetch_and_umax(&uval, 6u);
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// CHECK: atomicrmw umax i32* %uval, i32 6 seq_cst, align 4
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old = __sync_lock_test_and_set(&val, 7);
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// CHECK: atomicrmw xchg i32* %val, i32 7 seq_cst, align 4
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old = __sync_swap(&val, 8);
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// CHECK: atomicrmw xchg i32* %val, i32 8 seq_cst, align 4
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old = __sync_val_compare_and_swap(&val, 4, 1976);
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// CHECK: [[PAIR:%[a-z0-9_.]+]] = cmpxchg i32* %val, i32 4, i32 1976 seq_cst seq_cst, align 4
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// CHECK: extractvalue { i32, i1 } [[PAIR]], 0
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old = __sync_bool_compare_and_swap(&val, 4, 1976);
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// CHECK: [[PAIR:%[a-z0-9_.]+]] = cmpxchg i32* %val, i32 4, i32 1976 seq_cst seq_cst, align 4
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// CHECK: extractvalue { i32, i1 } [[PAIR]], 1
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old = __sync_fetch_and_and(&val, 0x9);
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// CHECK: atomicrmw and i32* %val, i32 9 seq_cst, align 4
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old = __sync_fetch_and_or(&val, 0xa);
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// CHECK: atomicrmw or i32* %val, i32 10 seq_cst, align 4
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old = __sync_fetch_and_xor(&val, 0xb);
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// CHECK: atomicrmw xor i32* %val, i32 11 seq_cst, align 4
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old = __sync_fetch_and_nand(&val, 0xc);
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// CHECK: atomicrmw nand i32* %val, i32 12 seq_cst, align 4
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old = __sync_add_and_fetch(&val, 1);
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// CHECK: atomicrmw add i32* %val, i32 1 seq_cst, align 4
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old = __sync_sub_and_fetch(&val, 2);
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// CHECK: atomicrmw sub i32* %val, i32 2 seq_cst, align 4
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old = __sync_and_and_fetch(&valc, 3);
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// CHECK: atomicrmw and i8* %valc, i8 3 seq_cst, align 1
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old = __sync_or_and_fetch(&valc, 4);
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// CHECK: atomicrmw or i8* %valc, i8 4 seq_cst, align 1
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old = __sync_xor_and_fetch(&valc, 5);
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// CHECK: atomicrmw xor i8* %valc, i8 5 seq_cst, align 1
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old = __sync_nand_and_fetch(&valc, 6);
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// CHECK: atomicrmw nand i8* %valc, i8 6 seq_cst, align 1
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__sync_val_compare_and_swap((void **)0, (void *)0, (void *)0);
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// CHECK: [[PAIR:%[a-z0-9_.]+]] = cmpxchg i32* null, i32 0, i32 0 seq_cst seq_cst, align 4
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// CHECK: extractvalue { i32, i1 } [[PAIR]], 0
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if ( __sync_val_compare_and_swap(&valb, 0, 1)) {
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// CHECK: [[PAIR:%[a-z0-9_.]+]] = cmpxchg i8* %valb, i8 0, i8 1 seq_cst seq_cst, align 1
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// CHECK: [[VAL:%[a-z0-9_.]+]] = extractvalue { i8, i1 } [[PAIR]], 0
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// CHECK: trunc i8 [[VAL]] to i1
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old = 42;
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}
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__sync_bool_compare_and_swap((void **)0, (void *)0, (void *)0);
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// CHECK: cmpxchg i32* null, i32 0, i32 0 seq_cst seq_cst, align 4
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__sync_lock_release(&val);
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// CHECK: store atomic i32 0, {{.*}} release, align 4
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__sync_lock_release(&ptrval);
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// CHECK: store atomic i32 0, {{.*}} release, align 4
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__sync_synchronize ();
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// CHECK: fence seq_cst
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return old;
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}
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// CHECK: @release_return
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void release_return(int *lock) {
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// Ensure this is actually returning void all the way through.
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return __sync_lock_release(lock);
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// CHECK: store atomic {{.*}} release, align 4
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}
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// rdar://8461279 - Atomics with address spaces.
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// CHECK: @addrspace
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void addrspace(int __attribute__((address_space(256))) * P) {
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__sync_bool_compare_and_swap(P, 0, 1);
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// CHECK: cmpxchg i32 addrspace(256)*{{.*}}, i32 0, i32 1 seq_cst seq_cst, align 4
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__sync_val_compare_and_swap(P, 0, 1);
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// CHECK: cmpxchg i32 addrspace(256)*{{.*}}, i32 0, i32 1 seq_cst seq_cst, align 4
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__sync_xor_and_fetch(P, 123);
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// CHECK: atomicrmw xor i32 addrspace(256)*{{.*}}, i32 123 seq_cst, align 4
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}
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