8043d5a964
The ability to specify alignment was recently added, and it's an important property which we should ensure is set as expected by Clang. (Especially before making further changes to Clang's code in this area.) But, because it's on the end of the lines, the existing tests all ignore it. Therefore, update all the tests to also verify the expected alignment for atomicrmw and cmpxchg. While I was in there, I also updated uses of 'load atomic' and 'store atomic', and added the memory ordering, where that was missing.
136 lines
7.3 KiB
C
136 lines
7.3 KiB
C
// RUN: %clang_cc1 -fms-extensions -triple x86_64-windows-msvc %s -emit-llvm -o - | FileCheck %s --check-prefix=X64
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// RUN: %clang_cc1 -fms-extensions -triple thumbv7-windows-msvc %s -emit-llvm -o - | FileCheck %s --check-prefix=ARM
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// RUN: %clang_cc1 -fms-extensions -triple aarch64-windows-msvc %s -emit-llvm -o - | FileCheck %s --check-prefix=ARM
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volatile unsigned char sink = 0;
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void test32(long *base, long idx) {
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sink = _bittest(base, idx);
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sink = _bittestandcomplement(base, idx);
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sink = _bittestandreset(base, idx);
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sink = _bittestandset(base, idx);
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sink = _interlockedbittestandreset(base, idx);
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sink = _interlockedbittestandset(base, idx);
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sink = _interlockedbittestandset(base, idx);
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}
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void test64(__int64 *base, __int64 idx) {
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sink = _bittest64(base, idx);
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sink = _bittestandcomplement64(base, idx);
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sink = _bittestandreset64(base, idx);
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sink = _bittestandset64(base, idx);
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sink = _interlockedbittestandreset64(base, idx);
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sink = _interlockedbittestandset64(base, idx);
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}
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#if defined(_M_ARM) || defined(_M_ARM64)
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void test_arm(long *base, long idx) {
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sink = _interlockedbittestandreset_acq(base, idx);
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sink = _interlockedbittestandreset_rel(base, idx);
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sink = _interlockedbittestandreset_nf(base, idx);
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sink = _interlockedbittestandset_acq(base, idx);
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sink = _interlockedbittestandset_rel(base, idx);
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sink = _interlockedbittestandset_nf(base, idx);
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}
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#endif
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// X64-LABEL: define dso_local void @test32(i32* %base, i32 %idx)
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// X64: call i8 asm sideeffect "btl $2, ($1)", "={@ccc},r,r,~{cc},~{memory},~{dirflag},~{fpsr},~{flags}"(i32* %{{.*}}, i32 {{.*}})
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// X64: call i8 asm sideeffect "btcl $2, ($1)", "={@ccc},r,r,~{cc},~{memory},~{dirflag},~{fpsr},~{flags}"(i32* %{{.*}}, i32 {{.*}})
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// X64: call i8 asm sideeffect "btrl $2, ($1)", "={@ccc},r,r,~{cc},~{memory},~{dirflag},~{fpsr},~{flags}"(i32* %{{.*}}, i32 {{.*}})
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// X64: call i8 asm sideeffect "btsl $2, ($1)", "={@ccc},r,r,~{cc},~{memory},~{dirflag},~{fpsr},~{flags}"(i32* %{{.*}}, i32 {{.*}})
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// X64: call i8 asm sideeffect "lock btrl $2, ($1)", "={@ccc},r,r,~{cc},~{memory},~{dirflag},~{fpsr},~{flags}"(i32* %{{.*}}, i32 {{.*}})
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// X64: call i8 asm sideeffect "lock btsl $2, ($1)", "={@ccc},r,r,~{cc},~{memory},~{dirflag},~{fpsr},~{flags}"(i32* %{{.*}}, i32 {{.*}})
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// X64-LABEL: define dso_local void @test64(i64* %base, i64 %idx)
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// X64: call i8 asm sideeffect "btq $2, ($1)", "={@ccc},r,r,~{cc},~{memory},~{dirflag},~{fpsr},~{flags}"(i64* %{{.*}}, i64 {{.*}})
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// X64: call i8 asm sideeffect "btcq $2, ($1)", "={@ccc},r,r,~{cc},~{memory},~{dirflag},~{fpsr},~{flags}"(i64* %{{.*}}, i64 {{.*}})
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// X64: call i8 asm sideeffect "btrq $2, ($1)", "={@ccc},r,r,~{cc},~{memory},~{dirflag},~{fpsr},~{flags}"(i64* %{{.*}}, i64 {{.*}})
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// X64: call i8 asm sideeffect "btsq $2, ($1)", "={@ccc},r,r,~{cc},~{memory},~{dirflag},~{fpsr},~{flags}"(i64* %{{.*}}, i64 {{.*}})
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// X64: call i8 asm sideeffect "lock btrq $2, ($1)", "={@ccc},r,r,~{cc},~{memory},~{dirflag},~{fpsr},~{flags}"(i64* %{{.*}}, i64 {{.*}})
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// X64: call i8 asm sideeffect "lock btsq $2, ($1)", "={@ccc},r,r,~{cc},~{memory},~{dirflag},~{fpsr},~{flags}"(i64* %{{.*}}, i64 {{.*}})
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// ARM-LABEL: define dso_local {{.*}}void @test32(i32* %base, i32 %idx)
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// ARM: %[[IDXHI:[^ ]*]] = ashr i32 %{{.*}}, 3
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// ARM: %[[BASE:[^ ]*]] = bitcast i32* %{{.*}} to i8*
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// ARM: %[[BYTEADDR:[^ ]*]] = getelementptr inbounds i8, i8* %[[BASE]], i32 %[[IDXHI]]
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// ARM: %[[IDX8:[^ ]*]] = trunc i32 %{{.*}} to i8
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// ARM: %[[IDXLO:[^ ]*]] = and i8 %[[IDX8]], 7
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// ARM: %[[BYTE:[^ ]*]] = load i8, i8* %[[BYTEADDR]], align 1
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// ARM: %[[BYTESHR:[^ ]*]] = lshr i8 %[[BYTE]], %[[IDXLO]]
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// ARM: %[[RES:[^ ]*]] = and i8 %[[BYTESHR]], 1
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// ARM: store volatile i8 %[[RES]], i8* @sink, align 1
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// ARM: %[[IDXHI:[^ ]*]] = ashr i32 %{{.*}}, 3
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// ARM: %[[BASE:[^ ]*]] = bitcast i32* %{{.*}} to i8*
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// ARM: %[[BYTEADDR:[^ ]*]] = getelementptr inbounds i8, i8* %[[BASE]], i32 %[[IDXHI]]
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// ARM: %[[IDX8:[^ ]*]] = trunc i32 %{{.*}} to i8
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// ARM: %[[IDXLO:[^ ]*]] = and i8 %[[IDX8]], 7
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// ARM: %[[MASK:[^ ]*]] = shl i8 1, %[[IDXLO]]
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// ARM: %[[BYTE:[^ ]*]] = load i8, i8* %[[BYTEADDR]], align 1
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// ARM: %[[NEWBYTE:[^ ]*]] = xor i8 %[[BYTE]], %[[MASK]]
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// ARM: store i8 %[[NEWBYTE]], i8* %[[BYTEADDR]], align 1
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// ARM: %[[BYTESHR:[^ ]*]] = lshr i8 %[[BYTE]], %[[IDXLO]]
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// ARM: %[[RES:[^ ]*]] = and i8 %[[BYTESHR]], 1
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// ARM: store volatile i8 %[[RES]], i8* @sink, align 1
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// ARM: %[[IDXHI:[^ ]*]] = ashr i32 %{{.*}}, 3
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// ARM: %[[BASE:[^ ]*]] = bitcast i32* %{{.*}} to i8*
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// ARM: %[[BYTEADDR:[^ ]*]] = getelementptr inbounds i8, i8* %[[BASE]], i32 %[[IDXHI]]
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// ARM: %[[IDX8:[^ ]*]] = trunc i32 %{{.*}} to i8
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// ARM: %[[IDXLO:[^ ]*]] = and i8 %[[IDX8]], 7
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// ARM: %[[MASK:[^ ]*]] = shl i8 1, %[[IDXLO]]
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// ARM: %[[BYTE:[^ ]*]] = load i8, i8* %[[BYTEADDR]], align 1
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// ARM: %[[NOTMASK:[^ ]*]] = xor i8 %[[MASK]], -1
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// ARM: %[[NEWBYTE:[^ ]*]] = and i8 %[[BYTE]], %[[NOTMASK]]
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// ARM: store i8 %[[NEWBYTE]], i8* %[[BYTEADDR]], align 1
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// ARM: %[[BYTESHR:[^ ]*]] = lshr i8 %[[BYTE]], %[[IDXLO]]
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// ARM: %[[RES:[^ ]*]] = and i8 %[[BYTESHR]], 1
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// ARM: store volatile i8 %[[RES]], i8* @sink, align 1
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// ARM: %[[IDXHI:[^ ]*]] = ashr i32 %{{.*}}, 3
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// ARM: %[[BASE:[^ ]*]] = bitcast i32* %{{.*}} to i8*
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// ARM: %[[BYTEADDR:[^ ]*]] = getelementptr inbounds i8, i8* %[[BASE]], i32 %[[IDXHI]]
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// ARM: %[[IDX8:[^ ]*]] = trunc i32 %{{.*}} to i8
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// ARM: %[[IDXLO:[^ ]*]] = and i8 %[[IDX8]], 7
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// ARM: %[[MASK:[^ ]*]] = shl i8 1, %[[IDXLO]]
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// ARM: %[[BYTE:[^ ]*]] = load i8, i8* %[[BYTEADDR]], align 1
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// ARM: %[[NEWBYTE:[^ ]*]] = or i8 %[[BYTE]], %[[MASK]]
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// ARM: store i8 %[[NEWBYTE]], i8* %[[BYTEADDR]], align 1
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// ARM: %[[BYTESHR:[^ ]*]] = lshr i8 %[[BYTE]], %[[IDXLO]]
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// ARM: %[[RES:[^ ]*]] = and i8 %[[BYTESHR]], 1
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// ARM: store volatile i8 %[[RES]], i8* @sink, align 1
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// ARM: %[[IDXHI:[^ ]*]] = ashr i32 %{{.*}}, 3
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// ARM: %[[BASE:[^ ]*]] = bitcast i32* %{{.*}} to i8*
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// ARM: %[[BYTEADDR:[^ ]*]] = getelementptr inbounds i8, i8* %[[BASE]], i32 %[[IDXHI]]
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// ARM: %[[IDX8:[^ ]*]] = trunc i32 %{{.*}} to i8
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// ARM: %[[IDXLO:[^ ]*]] = and i8 %[[IDX8]], 7
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// ARM: %[[MASK:[^ ]*]] = shl i8 1, %[[IDXLO]]
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// ARM: %[[NOTMASK:[^ ]*]] = xor i8 %[[MASK]], -1
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// ARM: %[[BYTE:[^ ]*]] = atomicrmw and i8* %[[BYTEADDR]], i8 %[[NOTMASK]] seq_cst, align 1
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// ARM: %[[BYTESHR:[^ ]*]] = lshr i8 %[[BYTE]], %[[IDXLO]]
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// ARM: %[[RES:[^ ]*]] = and i8 %[[BYTESHR]], 1
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// ARM: store volatile i8 %[[RES]], i8* @sink, align 1
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// ARM: %[[IDXHI:[^ ]*]] = ashr i32 %{{.*}}, 3
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// ARM: %[[BASE:[^ ]*]] = bitcast i32* %{{.*}} to i8*
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// ARM: %[[BYTEADDR:[^ ]*]] = getelementptr inbounds i8, i8* %[[BASE]], i32 %[[IDXHI]]
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// ARM: %[[IDX8:[^ ]*]] = trunc i32 %{{.*}} to i8
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// ARM: %[[IDXLO:[^ ]*]] = and i8 %[[IDX8]], 7
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// ARM: %[[MASK:[^ ]*]] = shl i8 1, %[[IDXLO]]
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// ARM: %[[BYTE:[^ ]*]] = atomicrmw or i8* %[[BYTEADDR]], i8 %[[MASK]] seq_cst, align 1
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// ARM: %[[BYTESHR:[^ ]*]] = lshr i8 %[[BYTE]], %[[IDXLO]]
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// ARM: %[[RES:[^ ]*]] = and i8 %[[BYTESHR]], 1
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// ARM: store volatile i8 %[[RES]], i8* @sink, align 1
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// Just look for the atomicrmw instructions.
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// ARM-LABEL: define dso_local {{.*}}void @test_arm(i32* %base, i32 %idx)
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// ARM: atomicrmw and i8* %{{.*}}, i8 {{.*}} acquire, align 1
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// ARM: atomicrmw and i8* %{{.*}}, i8 {{.*}} release, align 1
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// ARM: atomicrmw and i8* %{{.*}}, i8 {{.*}} monotonic, align 1
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// ARM: atomicrmw or i8* %{{.*}}, i8 {{.*}} acquire, align 1
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// ARM: atomicrmw or i8* %{{.*}}, i8 {{.*}} release, align 1
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// ARM: atomicrmw or i8* %{{.*}}, i8 {{.*}} monotonic, align 1
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