a8081ed8ff
Refer to RISCV [1], LoongArch also need delayed decision for ADD/SUB relocations. In handleAddSubRelocations, just return directly if SecA != SecB, handleFixup usually will finish the the rest of creating PCRel relocations works. Otherwise we emit relocs depends on whether relaxation is enabled. If not, we return true and avoid record ADD/SUB relocations. Now the two symbols separated by alignment directive will return without folding symbol offset in AttemptToFoldSymbolOffsetDifference, which has the same effect when relaxation is enabled. [1] https://reviews.llvm.org/D155357
286 lines
11 KiB
C++
286 lines
11 KiB
C++
//===-- LoongArchAsmBackend.cpp - LoongArch Assembler Backend -*- C++ -*---===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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// This file implements the LoongArchAsmBackend class.
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//
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//===----------------------------------------------------------------------===//
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#include "LoongArchAsmBackend.h"
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#include "LoongArchFixupKinds.h"
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#include "llvm/MC/MCAsmLayout.h"
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#include "llvm/MC/MCAssembler.h"
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#include "llvm/MC/MCContext.h"
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#include "llvm/MC/MCELFObjectWriter.h"
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#include "llvm/MC/MCValue.h"
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#include "llvm/Support/EndianStream.h"
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#define DEBUG_TYPE "loongarch-asmbackend"
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using namespace llvm;
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std::optional<MCFixupKind>
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LoongArchAsmBackend::getFixupKind(StringRef Name) const {
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if (STI.getTargetTriple().isOSBinFormatELF()) {
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auto Type = llvm::StringSwitch<unsigned>(Name)
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#define ELF_RELOC(X, Y) .Case(#X, Y)
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#include "llvm/BinaryFormat/ELFRelocs/LoongArch.def"
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#undef ELF_RELOC
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.Case("BFD_RELOC_NONE", ELF::R_LARCH_NONE)
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.Case("BFD_RELOC_32", ELF::R_LARCH_32)
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.Case("BFD_RELOC_64", ELF::R_LARCH_64)
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.Default(-1u);
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if (Type != -1u)
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return static_cast<MCFixupKind>(FirstLiteralRelocationKind + Type);
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}
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return std::nullopt;
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}
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const MCFixupKindInfo &
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LoongArchAsmBackend::getFixupKindInfo(MCFixupKind Kind) const {
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const static MCFixupKindInfo Infos[] = {
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// This table *must* be in the order that the fixup_* kinds are defined in
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// LoongArchFixupKinds.h.
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//
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// {name, offset, bits, flags}
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{"fixup_loongarch_b16", 10, 16, MCFixupKindInfo::FKF_IsPCRel},
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{"fixup_loongarch_b21", 0, 26, MCFixupKindInfo::FKF_IsPCRel},
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{"fixup_loongarch_b26", 0, 26, MCFixupKindInfo::FKF_IsPCRel},
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{"fixup_loongarch_abs_hi20", 5, 20, 0},
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{"fixup_loongarch_abs_lo12", 10, 12, 0},
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{"fixup_loongarch_abs64_lo20", 5, 20, 0},
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{"fixup_loongarch_abs64_hi12", 10, 12, 0},
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{"fixup_loongarch_tls_le_hi20", 5, 20, 0},
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{"fixup_loongarch_tls_le_lo12", 10, 12, 0},
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{"fixup_loongarch_tls_le64_lo20", 5, 20, 0},
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{"fixup_loongarch_tls_le64_hi12", 10, 12, 0},
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// TODO: Add more fixup kinds.
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};
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static_assert((std::size(Infos)) == LoongArch::NumTargetFixupKinds,
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"Not all fixup kinds added to Infos array");
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// Fixup kinds from .reloc directive are like R_LARCH_NONE. They
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// do not require any extra processing.
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if (Kind >= FirstLiteralRelocationKind)
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return MCAsmBackend::getFixupKindInfo(FK_NONE);
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if (Kind < FirstTargetFixupKind)
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return MCAsmBackend::getFixupKindInfo(Kind);
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assert(unsigned(Kind - FirstTargetFixupKind) < getNumFixupKinds() &&
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"Invalid kind!");
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return Infos[Kind - FirstTargetFixupKind];
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}
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static void reportOutOfRangeError(MCContext &Ctx, SMLoc Loc, unsigned N) {
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Ctx.reportError(Loc, "fixup value out of range [" + Twine(llvm::minIntN(N)) +
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", " + Twine(llvm::maxIntN(N)) + "]");
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}
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static uint64_t adjustFixupValue(const MCFixup &Fixup, uint64_t Value,
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MCContext &Ctx) {
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switch (Fixup.getTargetKind()) {
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default:
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llvm_unreachable("Unknown fixup kind");
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case FK_Data_1:
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case FK_Data_2:
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case FK_Data_4:
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case FK_Data_8:
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return Value;
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case LoongArch::fixup_loongarch_b16: {
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if (!isInt<18>(Value))
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reportOutOfRangeError(Ctx, Fixup.getLoc(), 18);
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if (Value % 4)
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Ctx.reportError(Fixup.getLoc(), "fixup value must be 4-byte aligned");
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return (Value >> 2) & 0xffff;
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}
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case LoongArch::fixup_loongarch_b21: {
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if (!isInt<23>(Value))
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reportOutOfRangeError(Ctx, Fixup.getLoc(), 23);
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if (Value % 4)
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Ctx.reportError(Fixup.getLoc(), "fixup value must be 4-byte aligned");
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return ((Value & 0x3fffc) << 8) | ((Value >> 18) & 0x1f);
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}
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case LoongArch::fixup_loongarch_b26: {
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if (!isInt<28>(Value))
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reportOutOfRangeError(Ctx, Fixup.getLoc(), 28);
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if (Value % 4)
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Ctx.reportError(Fixup.getLoc(), "fixup value must be 4-byte aligned");
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return ((Value & 0x3fffc) << 8) | ((Value >> 18) & 0x3ff);
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}
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case LoongArch::fixup_loongarch_abs_hi20:
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case LoongArch::fixup_loongarch_tls_le_hi20:
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return (Value >> 12) & 0xfffff;
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case LoongArch::fixup_loongarch_abs_lo12:
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case LoongArch::fixup_loongarch_tls_le_lo12:
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return Value & 0xfff;
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case LoongArch::fixup_loongarch_abs64_lo20:
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case LoongArch::fixup_loongarch_tls_le64_lo20:
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return (Value >> 32) & 0xfffff;
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case LoongArch::fixup_loongarch_abs64_hi12:
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case LoongArch::fixup_loongarch_tls_le64_hi12:
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return (Value >> 52) & 0xfff;
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}
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}
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void LoongArchAsmBackend::applyFixup(const MCAssembler &Asm,
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const MCFixup &Fixup,
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const MCValue &Target,
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MutableArrayRef<char> Data, uint64_t Value,
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bool IsResolved,
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const MCSubtargetInfo *STI) const {
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if (!Value)
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return; // Doesn't change encoding.
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MCFixupKind Kind = Fixup.getKind();
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if (Kind >= FirstLiteralRelocationKind)
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return;
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MCFixupKindInfo Info = getFixupKindInfo(Kind);
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MCContext &Ctx = Asm.getContext();
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// Apply any target-specific value adjustments.
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Value = adjustFixupValue(Fixup, Value, Ctx);
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// Shift the value into position.
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Value <<= Info.TargetOffset;
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unsigned Offset = Fixup.getOffset();
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unsigned NumBytes = alignTo(Info.TargetSize + Info.TargetOffset, 8) / 8;
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assert(Offset + NumBytes <= Data.size() && "Invalid fixup offset!");
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// For each byte of the fragment that the fixup touches, mask in the
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// bits from the fixup value.
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for (unsigned I = 0; I != NumBytes; ++I) {
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Data[Offset + I] |= uint8_t((Value >> (I * 8)) & 0xff);
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}
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}
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bool LoongArchAsmBackend::shouldForceRelocation(const MCAssembler &Asm,
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const MCFixup &Fixup,
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const MCValue &Target,
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const MCSubtargetInfo *STI) {
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if (Fixup.getKind() >= FirstLiteralRelocationKind)
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return true;
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switch (Fixup.getTargetKind()) {
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default:
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return STI->hasFeature(LoongArch::FeatureRelax);
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case FK_Data_1:
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case FK_Data_2:
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case FK_Data_4:
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case FK_Data_8:
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return !Target.isAbsolute();
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}
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}
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static inline std::pair<MCFixupKind, MCFixupKind>
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getRelocPairForSize(unsigned Size) {
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switch (Size) {
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default:
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llvm_unreachable("unsupported fixup size");
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case 6:
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return std::make_pair(
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MCFixupKind(FirstLiteralRelocationKind + ELF::R_LARCH_ADD6),
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MCFixupKind(FirstLiteralRelocationKind + ELF::R_LARCH_SUB6));
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case 8:
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return std::make_pair(
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MCFixupKind(FirstLiteralRelocationKind + ELF::R_LARCH_ADD8),
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MCFixupKind(FirstLiteralRelocationKind + ELF::R_LARCH_SUB8));
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case 16:
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return std::make_pair(
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MCFixupKind(FirstLiteralRelocationKind + ELF::R_LARCH_ADD16),
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MCFixupKind(FirstLiteralRelocationKind + ELF::R_LARCH_SUB16));
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case 32:
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return std::make_pair(
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MCFixupKind(FirstLiteralRelocationKind + ELF::R_LARCH_ADD32),
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MCFixupKind(FirstLiteralRelocationKind + ELF::R_LARCH_SUB32));
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case 64:
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return std::make_pair(
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MCFixupKind(FirstLiteralRelocationKind + ELF::R_LARCH_ADD64),
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MCFixupKind(FirstLiteralRelocationKind + ELF::R_LARCH_SUB64));
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}
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}
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bool LoongArchAsmBackend::writeNopData(raw_ostream &OS, uint64_t Count,
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const MCSubtargetInfo *STI) const {
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// We mostly follow binutils' convention here: align to 4-byte boundary with a
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// 0-fill padding.
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OS.write_zeros(Count % 4);
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// The remainder is now padded with 4-byte nops.
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// nop: andi r0, r0, 0
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for (; Count >= 4; Count -= 4)
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OS.write("\0\0\x40\x03", 4);
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return true;
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}
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bool LoongArchAsmBackend::handleAddSubRelocations(const MCAsmLayout &Layout,
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const MCFragment &F,
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const MCFixup &Fixup,
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const MCValue &Target,
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uint64_t &FixedValue) const {
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std::pair<MCFixupKind, MCFixupKind> FK;
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uint64_t FixedValueA, FixedValueB;
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const MCSection &SecA = Target.getSymA()->getSymbol().getSection();
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const MCSection &SecB = Target.getSymB()->getSymbol().getSection();
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// We need record relocation if SecA != SecB. Usually SecB is same as the
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// section of Fixup, which will be record the relocation as PCRel. If SecB
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// is not same as the section of Fixup, it will report error. Just return
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// false and then this work can be finished by handleFixup.
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if (&SecA != &SecB)
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return false;
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// In SecA == SecB case. If the linker relaxation is enabled, we need record
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// the ADD, SUB relocations. Otherwise the FixedValue has already been
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// calculated out in evaluateFixup, return true and avoid record relocations.
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if (!STI.hasFeature(LoongArch::FeatureRelax))
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return true;
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switch (Fixup.getKind()) {
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case llvm::FK_Data_1:
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FK = getRelocPairForSize(8);
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break;
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case llvm::FK_Data_2:
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FK = getRelocPairForSize(16);
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break;
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case llvm::FK_Data_4:
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FK = getRelocPairForSize(32);
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break;
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case llvm::FK_Data_8:
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FK = getRelocPairForSize(64);
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break;
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default:
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llvm_unreachable("unsupported fixup size");
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}
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MCValue A = MCValue::get(Target.getSymA(), nullptr, Target.getConstant());
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MCValue B = MCValue::get(Target.getSymB());
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auto FA = MCFixup::create(Fixup.getOffset(), nullptr, std::get<0>(FK));
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auto FB = MCFixup::create(Fixup.getOffset(), nullptr, std::get<1>(FK));
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auto &Asm = Layout.getAssembler();
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Asm.getWriter().recordRelocation(Asm, Layout, &F, FA, A, FixedValueA);
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Asm.getWriter().recordRelocation(Asm, Layout, &F, FB, B, FixedValueB);
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FixedValue = FixedValueA - FixedValueB;
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return true;
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}
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std::unique_ptr<MCObjectTargetWriter>
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LoongArchAsmBackend::createObjectTargetWriter() const {
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return createLoongArchELFObjectWriter(
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OSABI, Is64Bit, STI.hasFeature(LoongArch::FeatureRelax));
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}
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MCAsmBackend *llvm::createLoongArchAsmBackend(const Target &T,
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const MCSubtargetInfo &STI,
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const MCRegisterInfo &MRI,
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const MCTargetOptions &Options) {
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const Triple &TT = STI.getTargetTriple();
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uint8_t OSABI = MCELFObjectTargetWriter::getOSABI(TT.getOS());
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return new LoongArchAsmBackend(STI, OSABI, TT.isArch64Bit(), Options);
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}
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