7ce3d9228f
Generate a predicated variant of the last load/store in a group to avoid accessing OOB memory. Disable vector alignment on HVX prior to v62, since v62 does not have predicated vector loads.
35 lines
1.2 KiB
LLVM
35 lines
1.2 KiB
LLVM
; RUN: llc -march=hexagon -hexagon-hvx-widen=32 < %s | FileCheck %s
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target triple = "hexagon"
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; Test the the store mask is adjusted for gaps between sections. The
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; Vector Combine pass generates masked stores for chunks of 128 bytes.
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; The masked store must be shifted if the first store in a section
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; is not a multiple of 128 bytes. This test checks that two masks
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; are created, and the second mask is used in a masked store.
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; CHECK: [[REG:r[0-9]+]] = ##.LCPI0_1
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; CHECK: [[VREG1:v[0-9]+]] = vmem([[REG]]+#0)
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; CHECK: [[VREG2:v[0-9]+]] = vlalign([[VREG1]],v{{[0-9]+}},r{{[0-9]+}})
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; CHECK: [[QREG:q[0-3]+]] = vand([[VREG2]],r{{[0-9]+}})
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; CHECK: if ([[QREG]]) vmem({{.*}}) = v{{[0-9]+}}
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define dllexport void @f0(ptr %a0) local_unnamed_addr #0 {
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b0:
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br label %b1
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b1: ; preds = %b1, %b0
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%v0 = or i32 -1, 40
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%v1 = getelementptr inbounds i32, ptr %a0, i32 %v0
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store <8 x i32> undef, ptr %v1, align 32
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%v3 = or i32 0, 48
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%v4 = getelementptr inbounds i32, ptr %a0, i32 %v3
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store <8 x i32> undef, ptr %v4, align 64
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br i1 undef, label %b2, label %b1
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b2: ; preds = %b1
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ret void
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}
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attributes #0 = { "target-features"="+hvxv66,+hvx-length128b,-packets" }
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