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llvm-project/llvm/test/Transforms/CodeGenPrepare/AArch64
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zhongyunde 00443407 d6f4d5209f [CGP][AArch64] Rebase the common base offset for better ISel
When all the large const offsets masked with the same value from bit-12 to bit-23.
Fold
  add     x8, x0, #2031, lsl #12
  add     x8, x8, #960
  ldr     x9, [x8, x8]
  ldr     x8, [x8, #2056]

into
  add     x8, x0, #2031, lsl #12
  ldr     x9, [x8, #960]
  ldr     x8, [x8, #3016]
2023-12-05 09:01:41 +08:00
..
combine-address-mode.ll
…
free-zext.ll
…
gather-scatter-opt-inseltpoison.ll
…
gather-scatter-opt.ll
…
large-offset-gep.ll
[CGP][AArch64] Rebase the common base offset for better ISel
2023-12-05 09:01:41 +08:00
lit.local.cfg
[NFC][Py Reformat] Reformat lit.local.cfg python files in llvm
2023-05-17 17:03:15 +02:00
overflow-intrinsics.ll
…
sink-free-instructions-inseltpoison.ll
…
sink-free-instructions.ll
…
sink-gather-scatter-addressing.ll
[SVE][CodeGenPrepare] Sink address calculations that match SVE gather/scatter addressing modes. (#66996)
2023-10-11 13:20:08 +01:00
trunc-weird-user.ll
…
widen_switch.ll
…
zext-to-shuffle.ll
…
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