zhongyunde 00443407 d093aee1a3 [AArch64] Fix schedmodel pre/post-index loads and stores for TSV110 ...

Similar to D159254, this fixes the order of WriteAdr operands on
post/pre-inc loads/stores in the TSV110 scheduling model.

2023-10-12 21:42:50 +08:00

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A64FX

[SVE][InstrFormats] Explcitly set hasSideEffects for all SVE instructions.

2023-01-25 12:30:46 +00:00

Cortex

[AArch64] Fix postinc operands for Cortex-A57 scheduling

2023-10-12 10:05:45 +01:00

Cyclone

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Exynos

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Falkor

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HiSilicon

[AArch64] Fix schedmodel pre/post-index loads and stores for TSV110

2023-10-12 21:42:50 +08:00

Neoverse

[AArch64] Fix postinc operands for Neoverse-N2 scheduling

2023-10-11 17:57:42 +01:00

lit.local.cfg

[NFC][Py Reformat] Reformat lit.local.cfg python files in llvm

2023-05-17 17:03:15 +02:00