Tim Northover 6b98824a58 AArch64: emit fcmp ord %a, zeroinitializer as a single fcmeq. ...

Most "ord" checks need two real-world compares to implement, but this is the
canonical form of a "!isnan" check, which is equivalent to comparing the input
for equality against itself.

2022-12-07 19:17:30 +00:00

..

AArch64CallLowering.cpp

[Target] Use std::nullopt instead of None (NFC)

2022-12-02 20:36:06 -08:00

AArch64CallLowering.h

[AArch64][GlobalISel] Add support for sret demotion.

2022-07-05 15:23:47 -07:00

AArch64GlobalISelUtils.cpp

[Target] Use std::nullopt instead of None (NFC)

2022-12-02 20:36:06 -08:00

AArch64GlobalISelUtils.h

Remove unused #include "llvm/ADT/Optional.h"

2022-12-05 04:21:08 +00:00

AArch64InstructionSelector.cpp

Remove unused #include "llvm/ADT/Optional.h"

2022-12-05 04:21:08 +00:00

AArch64LegalizerInfo.cpp

[AArch64][GlobalISel] Make vector G_SEXT_INREG legal and allow combining.

2022-10-05 00:28:08 +01:00

AArch64LegalizerInfo.h

[AArch64][GlobalISel] Implement custom legalization for s32/s64 G_FCOPYSIGN

2022-09-28 16:03:22 -07:00

AArch64O0PreLegalizerCombiner.cpp

[GlobalISel] Allow prelegalizer combiners to have access to LegalizerInfo.

2022-10-03 07:36:18 +01:00

AArch64PostLegalizerCombiner.cpp

Revert "[AArch64][GlobalISel] Fold away lowered vector sign-extend of vector compares."

2022-10-04 11:03:02 +01:00

AArch64PostLegalizerLowering.cpp

AArch64: emit fcmp ord %a, zeroinitializer as a single fcmeq.

2022-12-07 19:17:30 +00:00

AArch64PostSelectOptimize.cpp

[AArch64][GlobalISel] Add a simple cross-regclass copy optimization post-selection.

2022-11-01 16:09:21 -07:00

AArch64PreLegalizerCombiner.cpp

[GlobalISel] Allow prelegalizer combiners to have access to LegalizerInfo.

2022-10-03 07:36:18 +01:00

AArch64RegisterBankInfo.cpp

[AArch64] SME2 Single-multi vector ternary int/FP 2 and 4 registers

2022-10-19 17:49:48 +01:00

AArch64RegisterBankInfo.h

[nfc][codegen] Move RegisterBank[Info].h under CodeGen

2022-03-01 21:53:25 -08:00