f6e7ad5604
Resizing operations (e.g. sign extension) in DAG can go from any width to any other width, e.g. i8 -> i32. If the input and the result differ by a factor larger than 2, the operation cannot be legal in HVX, since the only two legal vector sizes in HVX are a single vector and a pair of vectors. To simplify the legalization, such operations are expanded into steps that only double/halve the type size, so that each such step can be fully legalized on its own. The complication is that DAG will automatically fold these steps back into one, e.g. sext(sext) -> sext. To prevent that new HexagonISD nodes are introduced: TL_EXTEND and TL_TRUNCATE. Once legalized, these nodes are replaced with the original opcodes. The type legalization is now common to aext/sext/zext/trunc and Hexagon- specific ssat/usat nodes.
58 lines
1.8 KiB
LLVM
58 lines
1.8 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -march=hexagon < %s | FileCheck %s
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; Check that this compiles successfully.
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target datalayout = "e-m:e-p:32:32:32-a:0-n16:32-i64:64:64-i32:32:32-i16:16:16-i1:8:8-f32:32:32-f64:64:64-v32:32:32-v64:64:64-v512:512:512-v1024:1024:1024-v2048:2048:2048"
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target triple = "hexagon"
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@g0 = global <16 x i16> zeroinitializer, align 2
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define void @fred(<16 x i32> %a0, <16 x i32> %a1) #0 {
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; CHECK-LABEL: fred:
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; CHECK: // %bb.0: // %b0
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; CHECK-NEXT: {
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; CHECK-NEXT: r1:0 = combine(#-1,#32)
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; CHECK-NEXT: v2 = vxor(v2,v2)
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; CHECK-NEXT: q0 = vcmp.eq(v0.w,v1.w)
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; CHECK-NEXT: }
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; CHECK-NEXT: {
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; CHECK-NEXT: r7 = ##g0
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; CHECK-NEXT: q1 = vsetq(r0)
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; CHECK-NEXT: v0 = vmux(q0,v0,v2)
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; CHECK-NEXT: }
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; CHECK-NEXT: {
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; CHECK-NEXT: v30 = vand(q1,r1)
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; CHECK-NEXT: }
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; CHECK-NEXT: {
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; CHECK-NEXT: v0.h = vpacke(v0.w,v0.w)
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; CHECK-NEXT: }
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; CHECK-NEXT: {
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; CHECK-NEXT: v3 = vlalign(v2,v30,r7)
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; CHECK-NEXT: }
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; CHECK-NEXT: {
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; CHECK-NEXT: q2 = vand(v3,r1)
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; CHECK-NEXT: v1 = vlalign(v30,v2,r7)
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; CHECK-NEXT: }
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; CHECK-NEXT: {
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; CHECK-NEXT: q3 = vand(v1,r1)
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; CHECK-NEXT: v31 = vlalign(v2,v0,r7)
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; CHECK-NEXT: }
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; CHECK-NEXT: {
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; CHECK-NEXT: v0 = vlalign(v0,v2,r7)
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; CHECK-NEXT: if (q2) vmem(r7+#1) = v31
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; CHECK-NEXT: }
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; CHECK-NEXT: {
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; CHECK-NEXT: jumpr r31
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; CHECK-NEXT: if (q3) vmem(r7+#0) = v0
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; CHECK-NEXT: }
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b0:
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%v0 = icmp eq <16 x i32> %a0, %a1
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%v1 = select <16 x i1> %v0, <16 x i32> %a0, <16 x i32> zeroinitializer
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%v2 = trunc <16 x i32> %v1 to <16 x i16>
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store <16 x i16> %v2, <16 x i16>* @g0, align 2
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ret void
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}
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attributes #0 = { norecurse nounwind "target-cpu"="hexagonv65" "target-features"="+hvx-length64b,+hvxv65" }
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