017186294d
Vector alignment code was grouping all aligned loads together. In some cases the groups could become quite large causing a lot of spill to be generated. This will place the loads closer to where they are used, reducing the register pressure.
79 lines
3.0 KiB
LLVM
79 lines
3.0 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -march=hexagon < %s | FileCheck %s
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; In this testcase, when loads were moved close to users, they were actualy
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; moved right before the consuming stores. This was after the store group
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; was moved, so the loads and stores ended up being interleaved. This violated
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; the assumption in store realigning that all loads were available before the
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; first store, causing some code depending on the loads being inserted before
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; the load used.
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; Just make sure that this compiles ok.
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; Function Attrs: nounwind
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define void @f0(i16* noalias nocapture readonly %a0, i16* noalias nocapture %a1, i32 %a2) #0 {
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; CHECK-LABEL: f0:
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; CHECK: // %bb.0: // %b0
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; CHECK-NEXT: {
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; CHECK-NEXT: p0 = cmp.eq(r2,#0)
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; CHECK-NEXT: if (p0.new) jumpr:nt r31
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; CHECK-NEXT: }
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; CHECK-NEXT: .p2align 4
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; CHECK-NEXT: .LBB0_1: // %b2
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; CHECK-NEXT: // =>This Inner Loop Header: Depth=1
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; CHECK-NEXT: {
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; CHECK-NEXT: v0.cur = vmem(r0+#0)
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; CHECK-NEXT: vmem(r1+#0) = v0
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; CHECK-NEXT: }
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; CHECK-NEXT: {
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; CHECK-NEXT: v29.cur = vmem(r0+#1)
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; CHECK-NEXT: vmem(r1+#1) = v29
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; CHECK-NEXT: }
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; CHECK-NEXT: {
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; CHECK-NEXT: v30.cur = vmem(r0+#2)
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; CHECK-NEXT: vmem(r1+#2) = v30
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; CHECK-NEXT: }
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; CHECK-NEXT: {
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; CHECK-NEXT: r0 = add(r0,#256)
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; CHECK-NEXT: r1 = add(r1,#256)
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; CHECK-NEXT: v31.cur = vmem(r0+#3)
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; CHECK-NEXT: vmem(r1+#3) = v31
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; CHECK-NEXT: }
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; CHECK-NEXT: {
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; CHECK-NEXT: jump .LBB0_1
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; CHECK-NEXT: }
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b0:
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%v0 = icmp eq i32 %a2, 0
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br i1 %v0, label %b3, label %b1
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b1: ; preds = %b0
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%v1 = bitcast i16* %a1 to <16 x i32>*
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%v2 = bitcast i16* %a0 to <16 x i32>*
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br label %b2
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b2: ; preds = %b2, %b1
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%v3 = phi <16 x i32>* [ %v16, %b2 ], [ %v1, %b1 ]
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%v4 = phi <16 x i32>* [ %v11, %b2 ], [ %v2, %b1 ]
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%v5 = getelementptr inbounds <16 x i32>, <16 x i32>* %v4, i32 1
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%v6 = load <16 x i32>, <16 x i32>* %v4, align 64
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%v7 = getelementptr inbounds <16 x i32>, <16 x i32>* %v4, i32 2
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%v8 = load <16 x i32>, <16 x i32>* %v5, align 64
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%v9 = getelementptr inbounds <16 x i32>, <16 x i32>* %v4, i32 3
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%v10 = load <16 x i32>, <16 x i32>* %v7, align 64
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%v11 = getelementptr inbounds <16 x i32>, <16 x i32>* %v4, i32 4
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%v12 = load <16 x i32>, <16 x i32>* %v9, align 64
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%v13 = getelementptr inbounds <16 x i32>, <16 x i32>* %v3, i32 1
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store <16 x i32> %v6, <16 x i32>* %v3, align 64
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%v14 = getelementptr inbounds <16 x i32>, <16 x i32>* %v3, i32 2
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store <16 x i32> %v8, <16 x i32>* %v13, align 64
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%v15 = getelementptr inbounds <16 x i32>, <16 x i32>* %v3, i32 3
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store <16 x i32> %v10, <16 x i32>* %v14, align 64
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%v16 = getelementptr inbounds <16 x i32>, <16 x i32>* %v3, i32 4
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store <16 x i32> %v12, <16 x i32>* %v15, align 64
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br label %b2
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b3: ; preds = %b0
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ret void
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}
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attributes #0 = { nounwind "target-features"="+hvxv65,+hvx-length64b" }
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