Vector alignment code was grouping all aligned loads together. In some cases the groups could become quite large causing a lot of spill to be generated. This will place the loads closer to where they are used, reducing the register pressure.
72 lines
3.3 KiB
LLVM
72 lines
3.3 KiB
LLVM
; RUN: llc -march=hexagon < %s | FileCheck %s
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; One of the loads is only used in a PHI instruction. Make sure the PHI use
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; still counts as a user of the load (and that the load is not removed).
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; CHECK-LABEL: f0:
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; CHECK: = vmem({{.*}})
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; CHECK: = vmem({{.*}})
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target datalayout = "e-m:e-p:32:32:32-a:0-n16:32-i64:64:64-i32:32:32-i16:16:16-i1:8:8-f32:32:32-f64:64:64-v32:32:32-v64:64:64-v512:512:512-v1024:1024:1024-v2048:2048:2048"
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target triple = "hexagon"
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declare <16 x i32> @llvm.hexagon.V6.vmux(<64 x i1>, <16 x i32>, <16 x i32>) #0
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declare <16 x i32> @llvm.hexagon.V6.vmpyiewuh.acc(<16 x i32>, <16 x i32>, <16 x i32>) #0
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declare <16 x i32> @llvm.hexagon.V6.vand(<16 x i32>, <16 x i32>) #0
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declare <64 x i1> @llvm.hexagon.V6.vgtuw.and(<64 x i1>, <16 x i32>, <16 x i32>) #0
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declare <64 x i1> @llvm.hexagon.V6.pred.or(<64 x i1>, <64 x i1>) #0
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define <16 x i32> @f0(i8* %a0, i32 %a1) local_unnamed_addr #1 {
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b0:
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%v0 = getelementptr inbounds i8, i8* %a0, i32 576
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%v1 = bitcast i8* %a0 to <16 x i32>*
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%v2 = bitcast i8* %v0 to <16 x i32>*
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br label %b1
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b1: ; preds = %b4, %b0
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%v3 = phi i32 [ 0, %b0 ], [ %v23, %b4 ]
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%v4 = phi <16 x i32> [ poison, %b0 ], [ %v22, %b4 ]
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br i1 poison, label %b2, label %b3
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b2: ; preds = %b1
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%v5 = getelementptr inbounds <16 x i32>, <16 x i32>* %v1, i32 %v3
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%v6 = load <16 x i32>, <16 x i32>* %v5, align 64
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%v7 = getelementptr inbounds <16 x i32>, <16 x i32>* %v2, i32 %v3
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%v8 = load <16 x i32>, <16 x i32>* %v7, align 64
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%v9 = tail call <16 x i32> @llvm.hexagon.V6.vmpyiewuh.acc(<16 x i32> poison, <16 x i32> %v6, <16 x i32> %v6)
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br label %b4
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b3: ; preds = %b1
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br label %b4
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b4: ; preds = %b3, %b2
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%v10 = phi <16 x i32> [ %v9, %b2 ], [ poison, %b3 ]
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%v11 = phi <16 x i32> [ %v8, %b2 ], [ poison, %b3 ]
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%v12 = tail call <16 x i32> @llvm.hexagon.V6.vmux(<64 x i1> poison, <16 x i32> %v10, <16 x i32> %v4)
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%v13 = tail call <16 x i32> @llvm.hexagon.V6.vmux(<64 x i1> poison, <16 x i32> %v11, <16 x i32> poison)
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%v14 = or i32 %v3, 1
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%v15 = getelementptr inbounds <16 x i32>, <16 x i32>* %v2, i32 %v14
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%v16 = load <16 x i32>, <16 x i32>* %v15, align 64
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%v17 = tail call <16 x i32> @llvm.hexagon.V6.vmpyiewuh.acc(<16 x i32> poison, <16 x i32> %v13, <16 x i32> poison)
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%v18 = tail call <16 x i32> @llvm.hexagon.V6.vand(<16 x i32> %v12, <16 x i32> poison)
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%v19 = tail call <64 x i1> @llvm.hexagon.V6.vgtuw.and(<64 x i1> poison, <16 x i32> %v17, <16 x i32> poison)
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%v20 = tail call <64 x i1> @llvm.hexagon.V6.pred.or(<64 x i1> %v19, <64 x i1> poison)
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%v21 = tail call <64 x i1> @llvm.hexagon.V6.pred.or(<64 x i1> %v20, <64 x i1> poison)
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%v22 = tail call <16 x i32> @llvm.hexagon.V6.vmux(<64 x i1> %v21, <16 x i32> poison, <16 x i32> %v12)
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%v23 = add nuw nsw i32 %v3, 2
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%v24 = icmp slt i32 %v23, %a1
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br i1 %v24, label %b1, label %b5, !llvm.loop !1
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b5: ; preds = %b4
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ret <16 x i32> %v22
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}
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attributes #0 = { nocallback nofree nosync nounwind willreturn memory(none) }
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attributes #1 = { "target-features"="+hvx-length64b,+hvxv65,+v65,-long-calls" }
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!llvm.linker.options = !{!0}
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!0 = !{!"$.str.3", !".rodata.str1.1"}
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!1 = distinct !{!1, !2}
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!2 = !{!"llvm.loop.mustprogress"}
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