2509a3fc64
In all cases, if a "mov" alias exists, it is the canonical form of the instruction. Now that TableGen can support aliases containing syntax variants, we can enable them and improve the quality of the asm output. llvm-svn: 208874
34 lines
727 B
LLVM
34 lines
727 B
LLVM
; RUN: llc < %s -march=arm64 -arm64-neon-syntax=apple | FileCheck %s
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define zeroext i8 @f1(<16 x i8> %a) {
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; CHECK-LABEL: f1:
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; CHECK: mov.b w0, v0[3]
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; CHECK-NEXT: ret
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%vecext = extractelement <16 x i8> %a, i32 3
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ret i8 %vecext
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}
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define zeroext i16 @f2(<4 x i16> %a) {
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; CHECK-LABEL: f2:
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; CHECK: mov.h w0, v0[2]
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; CHECK-NEXT: ret
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%vecext = extractelement <4 x i16> %a, i32 2
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ret i16 %vecext
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}
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define i32 @f3(<2 x i32> %a) {
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; CHECK-LABEL: f3:
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; CHECK: mov.s w0, v0[1]
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; CHECK-NEXT: ret
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%vecext = extractelement <2 x i32> %a, i32 1
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ret i32 %vecext
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}
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define i64 @f4(<2 x i64> %a) {
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; CHECK-LABEL: f4:
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; CHECK: mov.d x0, v0[1]
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; CHECK-NEXT: ret
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%vecext = extractelement <2 x i64> %a, i32 1
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ret i64 %vecext
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}
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