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Code Issues Pull Requests Actions 6 Packages Projects Releases Wiki Activity
llvm-project/llvm/test/Regression/CodeGen/ARM
History
Rafael Espindola d11fb5d13b implement shl and sra
llvm-svn: 30191
2006-09-08 17:36:23 +00:00
..
argaddr.ll
add a "load effective address"
2006-08-17 17:09:40 +00:00
bits.ll
implement shl and sra
2006-09-08 17:36:23 +00:00
branch.ll
add the SETULT condition code
2006-09-03 13:19:16 +00:00
call.ll
implement function calling of functions with up to 4 arguments
2006-07-25 20:17:20 +00:00
dg.exp
…
hello.ll
use a 'register pressure reducing' scheduler
2006-08-04 12:48:42 +00:00
ldr.ll
select code like
2006-08-14 19:01:24 +00:00
long.ll
add support for returning 64bit values
2006-09-04 19:05:01 +00:00
ret0.ll
…
ret_arg1.ll
added some tests for argument passing
2006-06-01 22:01:25 +00:00
ret_arg2.ll
added some tests for argument passing
2006-06-01 22:01:25 +00:00
ret_arg3.ll
added some tests for argument passing
2006-06-01 22:01:25 +00:00
ret_arg4.ll
added some tests for argument passing
2006-06-01 22:01:25 +00:00
ret_arg5.ll
initial implementation of ARMRegisterInfo::eliminateFrameIndex
2006-06-18 00:08:07 +00:00
ret_void.ll
added some tests for argument passing
2006-06-01 22:01:25 +00:00
select.ll
fix select.ll to always test a select node
2006-09-08 12:52:50 +00:00
vargs2.ll
test case for varargs functions
2006-08-25 17:57:36 +00:00
vargs.ll
fix the spill code
2006-08-09 16:41:12 +00:00
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