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llvm-project/llvm/test/CodeGen/VE/Vector
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Kazushi (Jam) Marukawa adbb46ea65 [VE] Support load/store vm regsiters 
Support load/store vm registers to memory location as a first step.
As a next step, support load/store vm registers to stack location.
This patch also adds several regression tests for not only load/store
vm registers but also missing load/store for vr registers.

Reviewed By: efocht

Differential Revision: https://reviews.llvm.org/D128610
2022-07-01 08:25:24 +09:00
..
expand_single_elem_build_vec.ll
…
extract_elt.ll
…
fastcc_callee.ll
…
fastcc_caller.ll
…
feature_vpu.ll
…
insert_elt.ll
…
loadvm.ll
[VE] Support load/store vm regsiters
2022-07-01 08:25:24 +09:00
loadvr.ll
[VE] Support load/store vm regsiters
2022-07-01 08:25:24 +09:00
mask_binary.ll
[VE] v256i1 and|or|xor isel and tests
2022-02-14 08:47:06 +01:00
mask_broadcast.ll
[VE] v256i1 broadcast isel and tests
2022-02-15 12:40:51 +01:00
storevm.ll
[VE] Support load/store vm regsiters
2022-07-01 08:25:24 +09:00
storevr.ll
[VE] Support load/store vm regsiters
2022-07-01 08:25:24 +09:00
vec_add.ll
…
vec_and.ll
…
vec_broadcast.ll
…
vec_fcmp.ll
[VE] Enable v256 fcmp true|false tests
2022-02-18 13:26:18 +01:00
vec_fma.ll
[VE] v256f32|64 fma isel
2022-03-14 15:59:13 +01:00
vec_fneg.ll
[VE] v512|256 f32|64 fneg isel and tests
2022-03-16 11:31:26 +01:00
vec_gather.ll
[VE] v256.32|64 gather|scatter isel and tests
2022-03-14 10:38:56 +01:00
vec_icmp.ll
[VE] v256.32|64 setcc isel and tests
2022-02-08 13:20:55 +01:00
vec_load.ll
[VE] (masked) load|store v256.32|64 isel
2022-03-02 13:31:29 +01:00
vec_reduce_add.ll
[VE] Remove output to /dev/stdout
2022-03-16 11:42:09 -04:00
vec_reduce_and.ll
[VE] Remove output to /dev/stdout
2022-03-16 11:42:09 -04:00
vec_reduce_or.ll
[VE] Remove output to /dev/stdout
2022-03-16 11:42:09 -04:00
vec_reduce_smax.ll
[VE] Remove output to /dev/stdout
2022-03-16 11:42:09 -04:00
vec_reduce_xor.ll
[VE] Remove output to /dev/stdout
2022-03-16 11:42:09 -04:00
vec_scatter.ll
[VE] v256.32|64 gather|scatter isel and tests
2022-03-14 10:38:56 +01:00
vec_select.ll
[VE] select|vp.merge|vp.select v256 isel and tests
2022-01-17 15:58:54 +01:00
vec_store.ll
[VE] (masked) load|store v256.32|64 isel
2022-03-02 13:31:29 +01:00
vp_add.ll
…
vp_and.ll
…
vp_ashr.ll
…
vp_fadd_merge.ll
[VE] vp_select+vectorBinOp passthru isel and tests
2022-01-18 11:31:14 +01:00
vp_fadd.ll
[VE] FADD,FSUB,FMUL,FDIV v256f32|f64 isel and tests
2021-12-21 09:15:31 +01:00
vp_fdiv_merge.ll
[VE] vp_select+vectorBinOp passthru isel and tests
2022-01-18 11:31:14 +01:00
vp_fdiv.ll
[VE] FADD,FSUB,FMUL,FDIV v256f32|f64 isel and tests
2021-12-21 09:15:31 +01:00
vp_fma_merge.ll
[VE] v256f32|64 fma isel
2022-03-14 15:59:13 +01:00
vp_fma.ll
[VE] v256f32|64 fma isel
2022-03-14 15:59:13 +01:00
vp_fmul_merge.ll
[VE] vp_select+vectorBinOp passthru isel and tests
2022-01-18 11:31:14 +01:00
vp_fmul.ll
[VE] FADD,FSUB,FMUL,FDIV v256f32|f64 isel and tests
2021-12-21 09:15:31 +01:00
vp_fsub_merge.ll
[VE] vp_select+vectorBinOp passthru isel and tests
2022-01-18 11:31:14 +01:00
vp_fsub.ll
[VE] FADD,FSUB,FMUL,FDIV v256f32|f64 isel and tests
2021-12-21 09:15:31 +01:00
vp_gather.ll
[VE] v256.32|64 gather|scatter isel and tests
2022-03-14 10:38:56 +01:00
vp_lshr.ll
…
vp_merge.ll
[VE] select|vp.merge|vp.select v256 isel and tests
2022-01-17 15:58:54 +01:00
vp_mul.ll
…
vp_or.ll
…
vp_reduce_add.ll
[VE] Remove output to /dev/stdout
2022-03-16 11:42:09 -04:00
vp_reduce_and.ll
[VE] Remove output to /dev/stdout
2022-03-16 11:42:09 -04:00
vp_reduce_or.ll
[VE] Remove output to /dev/stdout
2022-03-16 11:42:09 -04:00
vp_reduce_smax.ll
[VE] Remove output to /dev/stdout
2022-03-16 11:42:09 -04:00
vp_reduce_xor.ll
[VE] Remove output to /dev/stdout
2022-03-16 11:42:09 -04:00
vp_scatter.ll
[VE] v256.32|64 gather|scatter isel and tests
2022-03-14 10:38:56 +01:00
vp_sdiv.ll
[VE] U|SDIV v256i32|64 isel and tests
2021-12-21 08:51:01 +01:00
vp_select.ll
[VE] select|vp.merge|vp.select v256 isel and tests
2022-01-17 15:58:54 +01:00
vp_shl.ll
…
vp_sra.ll
…
vp_srem.ll
Revert "[CodeGen] Place SDNode debug ID declaration under appropriate #if"
2022-04-06 20:32:53 +03:00
vp_srl.ll
…
vp_strided_load.ll
[VP] Preserve address space of pointer for strided load/store intrinsics.
2022-03-22 09:52:54 -07:00
vp_strided_store.ll
[VP] Preserve address space of pointer for strided load/store intrinsics.
2022-03-22 09:52:54 -07:00
vp_sub.ll
…
vp_udiv.ll
[VE] U|SDIV v256i32|64 isel and tests
2021-12-21 08:51:01 +01:00
vp_urem.ll
Revert "[CodeGen] Place SDNode debug ID declaration under appropriate #if"
2022-04-06 20:32:53 +03:00
vp_xor.ll
…