Matt Arsenault 1f283a60a4 Reapply "RegisterCoalescer: Add implicit-def of super register when coalescing SUBREG_TO_REG" ...

This reverts commit 9e50c6e6b5741895f58f3e530004052844b6af9f. A few assertion and verifier
errors have been fixed in the coalescer and allocator, so hopefully this sticks this time.

2023-12-06 23:07:22 +07:00

..

AArch64

Reapply "RegisterCoalescer: Add implicit-def of super register when coalescing SUBREG_TO_REG"

2023-12-06 23:07:22 +07:00

AMDGPU

[AMDGPU] Warn if 'amdgpu-waves-per-eu' target occupancy was not met (#74055)

2023-12-06 10:46:46 +01:00

ARC

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ARM

[ARM] Regenerate aapcs-hfa-code.ll

2023-12-06 12:09:30 +00:00

AVR

Revert "[CodeGen] Really renumber slot indexes before register allocation (#67038)"

2023-10-09 12:31:32 +01:00

BPF

[BPF] Attribute preserve_static_offset for structs

2023-12-05 19:21:42 +02:00

CSKY

[CSKY,test] Update switch.ll

2023-10-31 15:47:05 -07:00

DirectX

[DirectX] Update test after opt learned to infer datalayout (#70726)

2023-10-30 14:04:15 -07:00

Generic

[SelectionDAG] Add support to filter SelectionDAG dumps during ISel by function names (#72696)

2023-11-20 14:00:47 -08:00

Hexagon

[Tests] Add disjoint flag to some tests (NFC)

2023-12-05 14:09:36 +01:00

Inputs

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Lanai

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LoongArch

[LoongArch] Make ISD::VSELECT a legal operation with lsx/lasx

2023-12-06 16:43:38 +08:00

M68k

[M68k] Emit RTE for interrupt handler. (#72787)

2023-12-04 15:11:00 +08:00

Mips

[NFC][asan] Replace AsanInited/ENSURE_ASAN_INITED with TryAsanInitFromRtl (#74172)

2023-12-04 14:56:21 -08:00

MIR

MachineVerifier: Reject extra non-register operands on instructions (#73758)

2023-11-30 22:33:42 +09:00

MLRegAlloc

[mlgo] Fix test post PR #73899

2023-12-01 09:05:22 -08:00

MSP430

Revert "[CodeGen] Really renumber slot indexes before register allocation (#67038)"

2023-10-09 12:31:32 +01:00

NVPTX

[NVPTX] Lower 16xi8 and 8xi8 stores efficiently (#73646)

2023-12-01 11:00:01 +05:30

PowerPC

[Tests] Add disjoint flag to some tests (NFC)

2023-12-05 14:09:36 +01:00

RISCV

[RISCV] Support FrameIndex operands in getMemOperandsWithOffsetWidth / getMemOperandWithOffsetWidth (#73802)

2023-12-05 21:26:56 +00:00

SPARC

[Sparc] Remove duplicate ALU and SETHI instructions (NFCI) (#66851)

2023-10-10 20:34:20 +03:00

SPIRV

[SPIR-V] Add SPIRV-Tools for testing (#73044)

2023-12-04 12:24:51 -05:00

SystemZ

[SystemZ] Properly support 16 byte atomic int/fp types and ops. (#73134)

2023-12-05 17:17:21 +01:00

Thumb

Revert "[CodeGen] Really renumber slot indexes before register allocation (#67038)"

2023-10-09 12:31:32 +01:00

Thumb2

[Tests] Add disjoint flag to some tests (NFC)

2023-12-05 14:09:36 +01:00

VE

BlockFrequencyInfoImpl: Avoid big numbers, increase precision for small spreads

2023-10-24 20:27:39 -07:00

WebAssembly

[Tests] Add disjoint flag to some tests (NFC)

2023-12-05 14:09:36 +01:00

WinCFGuard

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WinEH

[CodeGen] Port WinEHPrepare to new pass manager (#74233)

2023-12-04 20:46:51 +07:00

X86

Reapply "RegisterCoalescer: Add implicit-def of super register when coalescing SUBREG_TO_REG"

2023-12-06 23:07:22 +07:00

XCore

[XCore] Set MaxAtomicSizeInBitsSupported to 0 (#74389)

2023-12-05 12:51:01 -05:00