Matt Arsenault 1fd1beea18 AMDGPU/GlobalISel: Fix translation of indirect calls

2020-07-22 13:13:21 -04:00

..

AArch64

[AArch64][SVE] Correctly allocate scavenging slot in presence of SVE.

2020-07-22 10:50:36 +01:00

AMDGPU

AMDGPU/GlobalISel: Fix translation of indirect calls

2020-07-22 13:13:21 -04:00

ARC

…

ARM

[Thumb] set code alignment for 16-bit load from constant pool

2020-07-22 10:12:41 +01:00

AVR

[AVR] Rewrite the function calling convention.

2020-06-23 21:36:18 +12:00

BPF

[llvm-readobj] Update tests because of changes in llvm-readobj behavior

2020-07-20 10:39:04 +01:00

Generic

[llc] (almost) remove --print-machineinstrs

2020-07-20 10:43:28 -07:00

Hexagon

[llc] (almost) remove --print-machineinstrs

2020-07-20 10:43:28 -07:00

Inputs

…

Lanai

…

Mips

[llvm-readobj] Update tests because of changes in llvm-readobj behavior

2020-07-20 10:39:04 +01:00

MIR

[llvm-readobj] Update tests because of changes in llvm-readobj behavior

2020-07-20 10:39:04 +01:00

MSP430

[MSP430] Declare comparison LibCalls as returning i16 instead of i32

2020-06-30 11:04:22 +03:00

NVPTX

[NVPTX] Fix for NVPTX module asm regression

2020-06-24 11:17:09 -07:00

PowerPC

[PowerPC] Add linker opt for PC Relative GOT indirect accesses

2020-07-22 09:08:23 -05:00

RISCV

[llvm-readobj] Update tests because of changes in llvm-readobj behavior

2020-07-20 10:39:04 +01:00

SPARC

[llvm-readobj] Update tests because of changes in llvm-readobj behavior

2020-07-20 10:39:04 +01:00

SystemZ

[SystemZ] Simplify knownbits.ll test

2020-06-30 16:31:59 +02:00

Thumb

…

Thumb2

[ARM] Add predicated add reduction patterns

2020-07-22 17:30:02 +01:00

VE

[VE] Support symbol with offset value

2020-07-01 23:55:27 +09:00

WebAssembly

[WebAssembly] Autogenerate checks in simd-offset.ll

2020-07-22 10:12:26 -07:00

WinCFGuard

…

WinEH

…

X86

[X86][AVX] getTargetShuffleMask - don't decode VBROADCAST(EXTRACT_SUBVECTOR(X,0)) patterns.

2020-07-21 21:55:44 +01:00

XCore

…