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llvm-project/llvm/lib/Target/AMDGPU
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Jay Foad cca6bc42d9 [AMDGPU] Use RegClass helper functions in getRegForInlineAsmConstraint. 
This avoids more long lists of register classes that have to be updated
every time we add a new one. NFC.

Differential Revision: https://reviews.llvm.org/D78570
2020-04-23 12:26:52 +01:00
..
AsmParser
[AMDGPU] Use SGPR instead of SReg classes
2020-04-23 11:45:22 +01:00
Disassembler
[AMDGPU] Add missing AReg classes
2020-04-22 13:10:37 +01:00
MCTargetDesc
[AMDGPU] Add 192-bit register classes
2020-04-22 13:10:37 +01:00
TargetInfo
CMake: Make most target symbols hidden by default
2020-01-14 19:46:52 -08:00
Utils
[AMDGPU] Use SGPR instead of SReg classes
2020-04-23 11:45:22 +01:00
AMDGPU.h
AMDGPU: Stop setting attributes based on TargetOptions
2020-03-27 13:13:43 -07:00
AMDGPU.td
AMDGPU: Add feature for fast f32 denormals
2020-04-04 20:01:24 -04:00
AMDGPUAliasAnalysis.cpp
…
AMDGPUAliasAnalysis.h
…
AMDGPUAlwaysInlinePass.cpp
AMDGPU: Hack out noinline on functions using LDS globals
2020-04-02 14:12:07 -04:00
AMDGPUAnnotateKernelFeatures.cpp
[llvm][NFC][CallSite] Remove Implementation uses of CallSite
2020-04-14 14:49:47 -07:00
AMDGPUAnnotateUniformValues.cpp
Sink all InitializePasses.h includes
2019-11-13 16:34:37 -08:00
AMDGPUArgumentUsageInfo.cpp
AMDGPU: Add flag to used fixed function ABI
2020-03-13 13:27:05 -07:00
AMDGPUArgumentUsageInfo.h
AMDGPU: Initial, crude support for indirect calls
2020-03-18 12:03:48 -04:00
AMDGPUAsmPrinter.cpp
[AMDGPU] Add 192-bit register classes
2020-04-22 13:10:37 +01:00
AMDGPUAsmPrinter.h
[AsmPrinter][MCStreamer] De-capitalize EmitInstruction and EmitCFI*
2020-02-13 22:08:55 -08:00
AMDGPUAtomicOptimizer.cpp
[AMDGPU] New llvm.amdgcn.ballot intrinsic
2020-03-31 10:35:39 +02:00
AMDGPUCallingConv.td
AMDGPU: Allow i16 shader arguments
2020-01-27 06:55:32 -08:00
AMDGPUCallLowering.cpp
[Alignment][NFC] Transition to inferAlignFromPtrInfo
2020-03-31 08:06:49 +00:00
AMDGPUCallLowering.h
[Alignment][NFC] Transition to inferAlignFromPtrInfo
2020-03-31 08:06:49 +00:00
AMDGPUCodeGenPrepare.cpp
[TTI] Clean up includes (NFC).
2020-04-19 20:11:59 +01:00
AMDGPUCombine.td
AMDGPU/GlobalISel: Combines for V_CVT_F32_UBYTE[0-3]
2020-04-13 19:18:19 -04:00
AMDGPUFeatures.td
AMDGPU: Remove denormal subtarget features
2020-04-02 17:17:12 -04:00
AMDGPUFixFunctionBitcasts.cpp
[CallSite removal][AMDGPU] Use CallBase instead of CallSite in AMDGPUFixFunctionBitcasts. NFC
2020-04-19 15:21:02 -07:00
AMDGPUFrameLowering.cpp
Use Align for TFL::TransientStackAlignment
2019-10-21 08:31:25 +00:00
AMDGPUFrameLowering.h
[Alignment][NFC] Deprecate Align::None()
2020-01-24 12:53:58 +01:00
AMDGPUGenRegisterBankInfo.def
AMDGPU/GlobalISel: Fix RegBankSelect for G_INSERT_VECTOR_ELT
2020-01-22 10:57:50 -05:00
AMDGPUGISel.td
[llvm] NFC: Fix trivial typo in rst and td files
2020-04-23 14:26:32 +09:00
AMDGPUGlobalISelUtils.cpp
AMDGPU/GlobalISel: Select G_SHUFFLE_VECTOR
2020-02-21 13:35:40 -05:00
AMDGPUGlobalISelUtils.h
AMDGPU/GlobalISel: Start selecting image intrinsics
2020-03-30 17:33:04 -04:00
AMDGPUHSAMetadataStreamer.cpp
[SVE] Add new VectorType subclasses
2020-04-22 08:59:01 -07:00
AMDGPUHSAMetadataStreamer.h
…
AMDGPUInline.cpp
[llvm][NFC] CallSite removal from inliner-related files
2020-04-13 21:28:58 -07:00
AMDGPUInstrInfo.cpp
[AMDGPU] Remove AMDGPURegisterInfo
2020-02-11 11:13:38 -08:00
AMDGPUInstrInfo.h
AMDGPU/GlobalISel: Change intrinsic ID for _L to _LZ opt
2020-04-01 13:03:02 -04:00
AMDGPUInstrInfo.td
[llvm] NFC: Fix trivial typo in rst and td files
2020-04-23 14:26:32 +09:00
AMDGPUInstructions.td
AMDGPU: Remove denormal subtarget features
2020-04-02 17:17:12 -04:00
AMDGPUInstructionSelector.cpp
AMDGPU: Use Register
2020-04-21 15:19:35 -04:00
AMDGPUInstructionSelector.h
AMDGPU/GlobalISel: Fix selection of scalar f64 G_FABS
2020-04-14 22:05:22 -04:00
AMDGPUISelDAGToDAG.cpp
[AMDGPU] Remove selectSGPRVectorRegClassID. NFC.
2020-04-21 16:29:21 +01:00
AMDGPUISelLowering.cpp
AMDGPU: Remove custom node for RSQ_LEGACY
2020-04-17 19:50:36 -04:00
AMDGPUISelLowering.h
AMDGPU: Remove custom node for RSQ_LEGACY
2020-04-17 19:50:36 -04:00
AMDGPULegalizerInfo.cpp
[GlobalISel][AMDGPU] add legalization for G_FREEZE
2020-04-17 16:44:46 +02:00
AMDGPULegalizerInfo.h
AMDGPU/GlobalISel: Legalize 64-bit G_UDIV/G_UREM
2020-03-30 10:57:37 -04:00
AMDGPULibCalls.cpp
AMDGPU: Stop setting attributes based on TargetOptions
2020-03-27 13:13:43 -07:00
AMDGPULibFunc.cpp
[TypeSize] Allow returning scalable size in implicit conversion to uint64_t
2020-03-15 13:48:49 +00:00
AMDGPULibFunc.h
Make llvm::StringRef to std::string conversions explicit.
2020-01-28 23:25:25 +01:00
AMDGPULowerIntrinsics.cpp
AMDGPU: Add flag to control mem intrinsic expansion
2020-02-03 14:26:01 -08:00
AMDGPULowerKernelArguments.cpp
Clean up usages of asserting vector getters in Type
2020-04-09 13:11:37 -07:00
AMDGPULowerKernelAttributes.cpp
…
AMDGPUMachineCFGStructurizer.cpp
[AMDGPU] Fixes -Wrange-loop-analysis warnings
2019-12-22 19:39:28 +01:00
AMDGPUMachineFunction.cpp
AMDGPU: Remove denormal subtarget features
2020-04-02 17:17:12 -04:00
AMDGPUMachineFunction.h
AMDGPU: Refactor treatment of denormal mode
2019-11-19 19:55:43 +05:30
AMDGPUMachineModuleInfo.cpp
…
AMDGPUMachineModuleInfo.h
…
AMDGPUMacroFusion.cpp
[AMDGPU] Extend macro fusion for ADDC and SUBB to SUBBREV
2020-03-11 17:59:21 +00:00
AMDGPUMacroFusion.h
…
AMDGPUMCInstLower.cpp
[AsmPrinter][MCStreamer] De-capitalize EmitInstruction and EmitCFI*
2020-02-13 22:08:55 -08:00
AMDGPUOpenCLEnqueuedBlockLowering.cpp
Avoid SmallString.h include in MD5.h, NFC
2020-02-26 09:10:24 -08:00
AMDGPUPerfHintAnalysis.cpp
[llvm][NFC][CallSite] Remove Implementation uses of CallSite
2020-04-14 14:49:47 -07:00
AMDGPUPerfHintAnalysis.h
…
AMDGPUPostLegalizerCombiner.cpp
AMDGPU/GlobalISel: Combines for V_CVT_F32_UBYTE[0-3]
2020-04-13 19:18:19 -04:00
AMDGPUPreLegalizerCombiner.cpp
AMDGPU/GlobalISel: Introduce post-legalize combiner
2020-02-24 22:12:12 -05:00
AMDGPUPrintfRuntimeBinding.cpp
[SVE] Add new VectorType subclasses
2020-04-22 08:59:01 -07:00
AMDGPUPromoteAlloca.cpp
Remove SequentialType from the type heirarchy.
2020-04-06 17:03:49 -07:00
AMDGPUPropagateAttributes.cpp
[AMDGPU] Propagate amdgpu-waves-per-eu to callees
2020-03-26 14:43:44 -07:00
AMDGPUPTNote.h
…
AMDGPURegisterBankInfo.cpp
GlobalISel: Fix casted unmerge of G_CONCAT_VECTORS
2020-04-13 22:03:05 -04:00
AMDGPURegisterBankInfo.h
AMDGPU/GlobalISel: Handle sbfe/ubfe intrinsic
2020-02-17 09:20:13 -05:00
AMDGPURegisterBanks.td
[AMDGPU] Add 192-bit register classes
2020-04-22 13:10:37 +01:00
AMDGPURewriteOutArguments.cpp
Remove "mask" operand from shufflevector.
2020-03-31 13:08:59 -07:00
AMDGPUSearchableTables.td
AMDGPU: llvm.amdgcn.writelane is a source of divergence
2020-02-12 09:12:56 +01:00
AMDGPUSubtarget.cpp
Provide operand indices to adjustSchedDependency
2020-04-17 11:08:44 +01:00
AMDGPUSubtarget.h
Provide operand indices to adjustSchedDependency
2020-04-17 11:08:44 +01:00
AMDGPUTargetMachine.cpp
Introduce fix-irreducible pass
2020-04-15 15:05:51 +05:30
AMDGPUTargetMachine.h
AMDGPU: Add flag to used fixed function ABI
2020-03-13 13:27:05 -07:00
AMDGPUTargetObjectFile.cpp
…
AMDGPUTargetObjectFile.h
…
AMDGPUTargetTransformInfo.cpp
[NFC][TTI] Explicit use of VectorType
2020-04-20 09:16:52 +01:00
AMDGPUTargetTransformInfo.h
[NFC][TTI] Explicit use of VectorType
2020-04-20 09:16:52 +01:00
AMDGPUUnifyDivergentExitNodes.cpp
[AMDGPU] Fix AMDGPUUnifyDivergentExitNodes
2020-03-18 16:49:30 +01:00
AMDGPUUnifyMetadata.cpp
[AMDGPU] Fixes -Wrange-loop-analysis warnings
2019-12-22 19:39:28 +01:00
AMDILCFGStructurizer.cpp
Sink all InitializePasses.h includes
2019-11-13 16:34:37 -08:00
AMDKernelCodeT.h
…
BUFInstructions.td
[llvm] NFC: Fix trivial typo in rst and td files
2020-04-23 14:26:32 +09:00
CaymanInstructions.td
AMDGPU/EG,CM: Implement fsqrt using recip(rsqrt(x)) instead of x * rsqrt(x)
2020-02-05 00:24:07 -05:00
CMakeLists.txt
[AMDGPU] Add SIPreEmitPeephole pass.
2020-03-25 15:35:35 +00:00
DSInstructions.td
[llvm] NFC: Fix trivial typo in rst and td files
2020-04-23 14:26:32 +09:00
EvergreenInstructions.td
[AMDGPU] Add ISD::FSHR -> ALIGNBIT support
2020-03-12 20:16:57 +00:00
FLATInstructions.td
[llvm] NFC: Fix trivial typo in rst and td files
2020-04-23 14:26:32 +09:00
GCNDPPCombine.cpp
[AMDGPU][DPP] Corrected DPP combiner
2019-11-20 15:56:45 +03:00
GCNHazardRecognizer.cpp
Make more use of MachineInstr::mayLoadOrStore.
2019-12-19 11:51:52 +00:00
GCNHazardRecognizer.h
…
GCNILPSched.cpp
Prune a LegacyDivergenceAnalysis and MachineLoopInfo include each
2019-10-19 01:31:09 +00:00
GCNIterativeScheduler.cpp
[AMDGPU] Add file headers for few files where it is missing.
2020-01-31 02:06:41 +05:30
GCNIterativeScheduler.h
[AMDGPU] Add file headers for few files where it is missing.
2020-01-31 02:06:41 +05:30
GCNMinRegStrategy.cpp
[AMDGPU] Add file headers for few files where it is missing.
2020-01-31 02:06:41 +05:30
GCNNSAReassign.cpp
AMDGPU/GFX10: Fix NSA reassign pass when operands are undef
2020-02-01 22:41:40 +01:00
GCNProcessors.td
…
GCNRegBankReassign.cpp
[AMDGPU] Stabilize sort order
2020-03-28 20:20:14 +01:00
GCNRegPressure.cpp
[AMDGPU] Fix assumption about LaneBitmask content
2020-02-19 09:07:11 -08:00
GCNRegPressure.h
Upgrade some instances of std::sort to llvm::sort. NFC.
2020-03-28 19:23:29 +01:00
GCNSchedStrategy.cpp
[AMDGPU] Remove dubious logic in bidirectional list scheduler
2020-02-28 21:35:34 +00:00
GCNSchedStrategy.h
[AMDGPU] Attempt to reschedule withou clustering
2020-01-27 10:27:16 -08:00
LLVMBuild.txt
…
MIMGInstructions.td
[llvm] NFC: Fix trivial typo in rst and td files
2020-04-23 14:26:32 +09:00
R600.td
…
R600AsmPrinter.cpp
[MC] Add MCStreamer::emitInt{8,16,32,64}
2020-02-29 09:40:21 -08:00
R600AsmPrinter.h
[AsmPrinter][MCStreamer] De-capitalize EmitInstruction and EmitCFI*
2020-02-13 22:08:55 -08:00
R600ClauseMergePass.cpp
…
R600ControlFlowFinalizer.cpp
[AMDGPU] Make use of divideCeil. NFC.
2020-03-26 16:11:35 +00:00
R600Defines.h
…
R600EmitClauseMarkers.cpp
…
R600ExpandSpecialInstrs.cpp
[AMDGPU] Split R600 and GCN subregs
2020-02-10 08:29:56 -08:00
R600FrameLowering.cpp
CodeGen: Use Register in TargetFrameLowering
2020-04-07 17:07:44 -04:00
R600FrameLowering.h
CodeGen: Use Register in TargetFrameLowering
2020-04-07 17:07:44 -04:00
R600InstrFormats.td
…
R600InstrInfo.cpp
CodeGen: Use Register in TargetFrameLowering
2020-04-07 17:07:44 -04:00
R600InstrInfo.h
Use MCRegister in copyPhysReg
2019-11-11 14:42:33 +05:30
R600Instructions.td
AMDGPU: Remove denormal subtarget features
2020-04-02 17:17:12 -04:00
R600ISelLowering.cpp
CodeGen: Use Register in TargetFrameLowering
2020-04-07 17:07:44 -04:00
R600ISelLowering.h
…
R600MachineFunctionInfo.cpp
…
R600MachineFunctionInfo.h
…
R600MachineScheduler.cpp
…
R600MachineScheduler.h
…
R600OpenCLImageTypeLoweringPass.cpp
…
R600OptimizeVectorRegisters.cpp
…
R600Packetizer.cpp
…
R600Processors.td
…
R600RegisterInfo.cpp
[TBLGEN] Allow to override RC weight
2020-02-14 15:49:52 -08:00
R600RegisterInfo.h
[TBLGEN] Allow to override RC weight
2020-02-14 15:49:52 -08:00
R600RegisterInfo.td
[TBLGEN] Allow to override RC weight
2020-02-14 15:49:52 -08:00
R600Schedule.td
…
R700Instructions.td
…
SIAddIMGInit.cpp
[AMDGPU] Split R600 and GCN subregs
2020-02-10 08:29:56 -08:00
SIAnnotateControlFlow.cpp
AMDGPU: Fix extra type mangling on llvm.amdgcn.if.break
2020-02-03 07:02:05 -08:00
SIDefines.h
[AMDGPU] Added MI bit IsDOT
2019-09-17 17:56:13 +00:00
SIFixSGPRCopies.cpp
[AMDGPU] Propagate AGPR RC from PHI to its PHI operands
2020-04-03 11:23:02 -07:00
SIFixupVectorISel.cpp
AMDGPU/GlobalISel: Skip DAG hack passes on selected functions
2020-02-17 08:33:17 -08:00
SIFixVGPRCopies.cpp
…
SIFoldOperands.cpp
[AMDGPU] Extend constant folding for logical operations
2020-04-07 14:37:16 -04:00
SIFormMemoryClauses.cpp
Sink all InitializePasses.h includes
2019-11-13 16:34:37 -08:00
SIFrameLowering.cpp
AMDGPU: Use Register
2020-04-21 15:19:35 -04:00
SIFrameLowering.h
CodeGen: Use Register in TargetFrameLowering
2020-04-07 17:07:44 -04:00
SIInsertSkips.cpp
[AMDGPU] Add SIPreEmitPeephole pass.
2020-03-25 15:35:35 +00:00
SIInsertWaitcnts.cpp
[AMDGPU] Fix vccz after v_readlane/v_readfirstlane to vcc_lo/hi
2020-01-28 10:52:17 +00:00
SIInstrFormats.td
[AMDGPU] Add a16 feature to gfx10
2020-02-10 09:04:23 +01:00
SIInstrInfo.cpp
[AMDGPU] copyPhysReg() for 16 bit SGPR subregs
2020-04-17 11:59:39 -07:00
SIInstrInfo.h
CodeGen: Convert some TII hooks to use Register
2020-04-03 14:52:54 -04:00
SIInstrInfo.td
[llvm] NFC: Fix trivial typo in rst and td files
2020-04-23 14:26:32 +09:00
SIInstructions.td
[llvm] NFC: Fix trivial typo in rst and td files
2020-04-23 14:26:32 +09:00
SIISelLowering.cpp
[AMDGPU] Use RegClass helper functions in getRegForInlineAsmConstraint.
2020-04-23 12:26:52 +01:00
SIISelLowering.h
DAG: Fix wrong legality check for ISD::FMAD
2020-04-13 10:25:39 -07:00
SILoadStoreOptimizer.cpp
[AMDGPU] Use SGPR instead of SReg classes
2020-04-23 11:45:22 +01:00
SILowerControlFlow.cpp
[AMDGPU] Limit endcf-collapase to simple if
2020-04-07 10:27:23 -07:00
SILowerI1Copies.cpp
AMDGPU/GlobalISel: Skip DAG hack passes on selected functions
2020-02-17 08:33:17 -08:00
SILowerSGPRSpills.cpp
[AMDGPU] Define 16 bit SGPR subregs
2020-04-16 10:31:39 -07:00
SIMachineFunctionInfo.cpp
[Alignment][NFC] Use more Align versions of various functions
2020-04-02 09:00:53 +00:00
SIMachineFunctionInfo.h
[AMDGPU] Add Scratch Wave Offset to Scratch Buffer Descriptor in entry functions
2020-03-19 15:35:16 -04:00
SIMachineScheduler.cpp
[AMDGPU] Use generated RegisterPressureSets enum
2020-02-18 10:34:03 -08:00
SIMachineScheduler.h
[AMDGPU] Use generated RegisterPressureSets enum
2020-02-18 10:34:03 -08:00
SIMemoryLegalizer.cpp
[AMDGPU] Bundle loads before post-RA scheduler
2020-01-24 11:33:38 -08:00
SIModeRegister.cpp
…
SIOptimizeExecMasking.cpp
AMDGPU: Use Register
2019-12-27 16:53:21 -05:00
SIOptimizeExecMaskingPreRA.cpp
[AMDGPU] Don't assert on partial exec copy
2020-04-12 21:14:36 -07:00
SIPeepholeSDWA.cpp
Fix unused function warning (PR44808)
2020-02-12 15:12:48 +01:00
SIPostRABundler.cpp
[AMDGPU] Drop const for value that is copied (NFC).
2020-03-30 10:59:59 +01:00
SIPreAllocateWWMRegs.cpp
Sink all InitializePasses.h includes
2019-11-13 16:34:37 -08:00
SIPreEmitPeephole.cpp
[AMDGPU] Add SIPreEmitPeephole pass.
2020-03-25 15:35:35 +00:00
SIProgramInfo.h
[AMDGPU] separate accounting for agprs
2019-10-02 00:26:58 +00:00
SIRegisterInfo.cpp
[AMDGPU] Use SGPR instead of SReg classes
2020-04-23 11:45:22 +01:00
SIRegisterInfo.h
[AMDGPU] Remove selectSGPRVectorRegClassID. NFC.
2020-04-21 16:29:21 +01:00
SIRegisterInfo.td
[AMDGPU] Use SGPR instead of SReg classes
2020-04-23 11:45:22 +01:00
SIRemoveShortExecBranches.cpp
[AMDGPU] Don't remove short branches over kills
2020-02-03 09:26:52 +00:00
SISchedule.td
[llvm] NFC: Fix trivial typo in rst and td files
2020-04-23 14:26:32 +09:00
SIShrinkInstructions.cpp
AMDGPU: Use early return
2020-04-07 13:48:00 -04:00
SIWholeQuadMode.cpp
[AMDGPU] Fix whole wavefront mode
2020-03-17 17:23:23 +01:00
SMInstructions.td
[llvm] NFC: Fix trivial typo in rst and td files
2020-04-23 14:26:32 +09:00
SOPInstructions.td
[llvm] NFC: Fix trivial typo in rst and td files
2020-04-23 14:26:32 +09:00
VIInstrFormats.td
…
VIInstructions.td
[llvm] NFC: Fix trivial typo in rst and td files
2020-04-23 14:26:32 +09:00
VOP1Instructions.td
[llvm] NFC: Fix trivial typo in rst and td files
2020-04-23 14:26:32 +09:00
VOP2Instructions.td
[llvm] NFC: Fix trivial typo in rst and td files
2020-04-23 14:26:32 +09:00
VOP3Instructions.td
[llvm] NFC: Fix trivial typo in rst and td files
2020-04-23 14:26:32 +09:00
VOP3PInstructions.td
[llvm] NFC: Fix trivial typo in rst and td files
2020-04-23 14:26:32 +09:00
VOPCInstructions.td
[llvm] NFC: Fix trivial typo in rst and td files
2020-04-23 14:26:32 +09:00
VOPInstructions.td
[llvm] NFC: Fix trivial typo in rst and td files
2020-04-23 14:26:32 +09:00