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llvm-project/llvm/test/CodeGen
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Vikram Hegde 225fc4f356
[AMDGPU][SDAG] Try folding "lshr i64 + mad" to "mad_u64_u32" (#119218) 
The intention is to use a "copy" instead of a "sub" to handle the high
parts of 64-bit multiply for this specific case.

This unlocks copy prop use cases where the copy can be reused by later
multiply+add sequences if possible.

Fixes: SWDEV-487672, SWDEV-487669
2025-01-17 11:09:39 +05:30
..
AArch64
[MachineCP] Correctly handle register masks and sub-registers (#122734)
2025-01-16 09:39:27 +00:00
AMDGPU
[AMDGPU][SDAG] Try folding "lshr i64 + mad" to "mad_u64_u32" (#119218)
2025-01-17 11:09:39 +05:30
ARC
[ARC,test] Change llc -march= to -mtriple=
2024-12-15 12:29:53 -08:00
ARM
[CodeGenPrepare] Replace undef use with poison [NFC] (#123111)
2025-01-16 08:17:55 +00:00
AVR
[AVR] Wrap out-of-bounds relative jumps (#118015)
2024-12-27 11:44:55 +08:00
BPF
[BPF,test] Change llc -march= to -mtriple=
2024-12-15 11:04:24 -08:00
CSKY
…
DirectX
[HLSL][SPIRV][DXIL] Implement WaveActiveSum intrinsic (#118580)
2025-01-16 10:35:23 -08:00
Generic
[NFC][SelectionDAG] Replace generic @llvm.expect.with.probability codegen test with X86 test (#117848)
2024-12-01 17:46:08 -05:00
Hexagon
[Hexagon] Omit calls to specialized {float,fix} routines (#117423)
2025-01-15 14:21:48 -06:00
Inputs
…
Lanai
[test] Remove redundant -march= when target triple is specified in IR
2024-12-15 12:42:17 -08:00
LoongArch
Revert "[MachineLICM] Use RegisterClassInfo::getRegPressureSetLimit (#119826)"
2025-01-10 09:05:06 +01:00
M68k
[M68k,MSP430,test] Change llc -march= to -mtriple=
2024-12-15 10:09:30 -08:00
Mips
[MC][Mips] Add MipsWinCOFFObjectWriter/MipsWinCOFFStreamer (#114611)
2024-12-20 17:31:38 +08:00
MIR
Reapply "[aarch64][win] Add support for import call optimization (equivalent to MSVC /d2ImportCallOptimization) (#121516)" (#122777)
2025-01-13 14:00:14 -08:00
MLRegAlloc
…
MSP430
[M68k,MSP430,test] Change llc -march= to -mtriple=
2024-12-15 10:09:30 -08:00
NVPTX
[NVPTX] Improve support for {ex2,lg2}.approx (#120519)
2025-01-16 12:21:32 -08:00
PowerPC
[llvm] Mark scavenging spill-slots as *spilled* stack objects. (#122673)
2025-01-14 10:18:31 +02:00
RISCV
[RISCV] Allow non-loop invariant steps in RISCVGatherScatterLowering (#122244)
2025-01-17 08:58:56 +08:00
SPARC
[Sparc,test] Change llc -march= to -mtriple=
2024-12-15 10:29:34 -08:00
SPIRV
[HLSL][SPIRV][DXIL] Implement WaveActiveSum intrinsic (#118580)
2025-01-16 10:35:23 -08:00
SystemZ
[CodeGen] @llvm.experimental.stackmap make operands immediate (#117932)
2024-12-11 17:41:19 +08:00
Thumb
Reland "[ARM] Stop gluing ALU nodes to branches / selects" (#118887)
2024-12-07 10:14:36 +03:00
Thumb2
Revert "[MachineLICM] Use RegisterClassInfo::getRegPressureSetLimit (#119826)"
2025-01-10 09:05:06 +01:00
VE
[VE,test] Change llc -march= to -mtriple=
2024-12-15 10:24:14 -08:00
WebAssembly
[WebAssembly] Add -wasm-use-legacy-eh option (#122158)
2025-01-09 22:36:10 -08:00
WinCFGuard
…
WinEH
[WinEH] Take musttail calls into account when unlinking eh records (#119702)
2024-12-13 09:16:52 +01:00
X86
[X86] vector-compress.ll - regenerate with missing AVX2 test coverage
2025-01-16 14:17:33 +00:00
XCore
[XCore,test] Change llc -march= to -mtriple=
2024-12-15 10:31:38 -08:00
Xtensa
[CodeGen] Clean up tests that depend on implicit .text in MCAsmStreamer
2024-12-22 21:11:32 -08:00