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instructions in the legalized DAG, and leverage it to combine long sequences of instructions to PSHUFB. Eventually, the other x86-instruction-specific shuffle combines will probably all be driven out of this routine. But the real motivation is to detect after we have fully legalized and optimized a shuffle to the minimal number of x86 instructions whether it is profitable to replace the chain with a fully generic PSHUFB instruction even though doing so requires either a load from a constant pool or tying up a register with the mask. While the Intel manuals claim it should be used when it replaces 5 or more instructions (!!!!) my experience is that it is actually very fast on modern chips, and so I've gon with a much more aggressive model of replacing any sequence of 3 or more instructions. I've also taught it to do some basic canonicalization to special-purpose instructions which have smaller encodings than their generic counterparts. There are still quite a few FIXMEs here, and I've not yet implemented support for lowering blends with PSHUFB (where its power really shines due to being able to zero out lanes), but this starts implementing real PSHUFB support even when using the new, fancy shuffle lowering. =] llvm-svn: 214042
134 lines
4.6 KiB
LLVM
134 lines
4.6 KiB
LLVM
; RUN: llc < %s -mtriple=x86_64-apple-darwin -mcpu=corei7-avx -mattr=+avx | FileCheck %s
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@x = common global <8 x float> zeroinitializer, align 32
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@y = common global <4 x double> zeroinitializer, align 32
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@z = common global <4 x float> zeroinitializer, align 16
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define void @zero128() nounwind ssp {
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entry:
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; CHECK: vxorps
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; CHECK: vmovaps
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store <4 x float> zeroinitializer, <4 x float>* @z, align 16
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ret void
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}
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define void @zero256() nounwind ssp {
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entry:
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; CHECK: vxorps
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; CHECK: vmovaps
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; CHECK: vmovaps
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store <8 x float> zeroinitializer, <8 x float>* @x, align 32
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store <4 x double> zeroinitializer, <4 x double>* @y, align 32
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ret void
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}
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; CHECK: vpcmpeqd
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; CHECK: vinsertf128 $1
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define void @ones([0 x float]* nocapture %RET, [0 x float]* nocapture %aFOO) nounwind {
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allocas:
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%ptr2vec615 = bitcast [0 x float]* %RET to <8 x float>*
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store <8 x float> <float 0xFFFFFFFFE0000000, float 0xFFFFFFFFE0000000, float
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0xFFFFFFFFE0000000, float 0xFFFFFFFFE0000000, float 0xFFFFFFFFE0000000, float
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0xFFFFFFFFE0000000, float 0xFFFFFFFFE0000000, float 0xFFFFFFFFE0000000>, <8 x
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float>* %ptr2vec615, align 32
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ret void
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}
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; CHECK: vpcmpeqd
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; CHECK: vinsertf128 $1
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define void @ones2([0 x i32]* nocapture %RET, [0 x i32]* nocapture %aFOO) nounwind {
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allocas:
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%ptr2vec615 = bitcast [0 x i32]* %RET to <8 x i32>*
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store <8 x i32> <i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1>, <8 x i32>* %ptr2vec615, align 32
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ret void
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}
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;;; Just make sure this doesn't crash
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; CHECK: _ISelCrash
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define <4 x i64> @ISelCrash(<4 x i64> %a) nounwind uwtable readnone ssp {
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entry:
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%shuffle = shufflevector <4 x i64> %a, <4 x i64> undef, <4 x i32> <i32 2, i32 3, i32 4, i32 4>
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ret <4 x i64> %shuffle
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}
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;;;
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;;; Check that some 256-bit vectors are xformed into 128 ops
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; CHECK: _A
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; CHECK: vshufpd $1
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; CHECK-NEXT: vextractf128 $1
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; CHECK-NEXT: vshufpd $1
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; CHECK-NEXT: vinsertf128 $1
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define <4 x i64> @A(<4 x i64> %a, <4 x i64> %b) nounwind uwtable readnone ssp {
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entry:
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%shuffle = shufflevector <4 x i64> %a, <4 x i64> %b, <4 x i32> <i32 1, i32 0, i32 7, i32 6>
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ret <4 x i64> %shuffle
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}
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; CHECK: _B
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; CHECK: vshufpd $1, %ymm
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define <4 x i64> @B(<4 x i64> %a, <4 x i64> %b) nounwind uwtable readnone ssp {
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entry:
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%shuffle = shufflevector <4 x i64> %a, <4 x i64> %b, <4 x i32> <i32 1, i32 undef, i32 undef, i32 6>
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ret <4 x i64> %shuffle
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}
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; CHECK: movlhps
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; CHECK-NEXT: vextractf128 $1
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; CHECK-NEXT: movlhps
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; CHECK-NEXT: vinsertf128 $1
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define <4 x i64> @C(<4 x i64> %a, <4 x i64> %b) nounwind uwtable readnone ssp {
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entry:
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%shuffle = shufflevector <4 x i64> %a, <4 x i64> %b, <4 x i32> <i32 undef, i32 0, i32 undef, i32 6>
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ret <4 x i64> %shuffle
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}
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; CHECK: vpshufd $-96
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; CHECK: vpunpckhdq
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; CHECK: vinsertf128 $1
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define <8 x i32> @D(<8 x i32> %a, <8 x i32> %b) nounwind uwtable readnone ssp {
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entry:
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%shuffle = shufflevector <8 x i32> %a, <8 x i32> %b, <8 x i32> <i32 0, i32 0, i32 2, i32 2, i32 10, i32 10, i32 11, i32 11>
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ret <8 x i32> %shuffle
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}
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;;; Don't crash on movd
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; CHECK: _VMOVZQI2PQI
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; CHECK: vmovd (%
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define <8 x i32> @VMOVZQI2PQI([0 x float]* nocapture %aFOO) nounwind {
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allocas:
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%ptrcast.i33.i = bitcast [0 x float]* %aFOO to i32*
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%val.i34.i = load i32* %ptrcast.i33.i, align 4
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%ptroffset.i22.i992 = getelementptr [0 x float]* %aFOO, i64 0, i64 1
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%ptrcast.i23.i = bitcast float* %ptroffset.i22.i992 to i32*
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%val.i24.i = load i32* %ptrcast.i23.i, align 4
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%updatedret.i30.i = insertelement <8 x i32> undef, i32 %val.i34.i, i32 1
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ret <8 x i32> %updatedret.i30.i
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}
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;;;; Don't crash on fneg
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; rdar://10566486
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; CHECK: fneg
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; CHECK: vxorps
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define <16 x float> @fneg(<16 x float> %a) nounwind {
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%1 = fsub <16 x float> <float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00>, %a
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ret <16 x float> %1
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}
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;;; Don't crash on build vector
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; CHECK: @build_vec_16x16
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; CHECK: vmovd
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define <16 x i16> @build_vec_16x16(i16 %a) nounwind readonly {
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%res = insertelement <16 x i16> <i16 undef, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0>, i16 %a, i32 0
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ret <16 x i16> %res
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}
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;;; Check that VMOVPQIto64rr generates the assembly string "vmovq". Previously
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;;; an incorrect mnemonic of "movd" was printed for this instruction.
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; CHECK: VMOVPQIto64rr
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; CHECK: vmovq
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define i64 @VMOVPQIto64rr(<2 x i64> %a) {
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entry:
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%vecext.i = extractelement <2 x i64> %a, i32 0
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ret i64 %vecext.i
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}
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