7a0f7dbf2d
Reapply of a22d1c2225543aa9ae7882f6b1a97ee7b2c95574. Using this PR for pre-merge CI. Instead of relying on any pass manager to schedule Polly's passes, add Polly's own pipeline manager which is seen as a monolithic pass in LLVM's pass manager. Polly's former passes are now phases of the new PhaseManager component. Relying on LLVM's pass manager (the legacy as well as the New Pass Manager) to manage Polly's phases never was a good fit that the PhaseManager resolves: * Polly passes were modifying analysis results, in particular RegionInfo and ScopInfo. This means that there was not just one unique and "definite" analysis result, the actual result depended on which analyses ran prior, and the pass manager was not allowed to throw away cached analyses or prior SCoP optimizations would have been forgotten. The LLVM pass manger's persistance of analysis results is not contractual but designed for caching. * Polly depends on a particular execution order of passes and regions (e.g. regression tests, invalidation of consecutive SCoPs). LLVM's pass manager does not guarantee any excecution order. * Polly does not completely preserve DominatorTree, RegionInfo, LoopInfo, or ScalarEvolution, but only as-needed for Polly's own uses. Because the ScopDetection object stores references to those analyses, it still had to lie to the pass manager that they would be preserved, or the pass manager would have released and recomputed the invalidated analysis objects that ScopDetection/ScopInfo was still referencing. To ensure that no non-Polly pass would see these not-completely-preserved analyses, all analyses still had to be thrown away after the ScopPassManager, respectively with a BarrierNoopPass in case of the LPM. * The NPM's PassInstrumentation wraps the IR unit into an `llvm::Any` object, but implementations such as PrintIRInstrumentation call llvm_unreachable on encountering an unknown IR unit, such as SCoPs, with no extension points to add support. Hence LLVM crashes when dumping IR between SCoP passes (such as `-print-before-changed` with Polly being active). The new PhaseManager uses some command line options that previously belonged to Polly's legacy passes, such as `-polly-print-detect` (so the option will continue to work). Hence the LPM support is incompatible with the new approach and support for it is removed.
106 lines
4.3 KiB
LLVM
106 lines
4.3 KiB
LLVM
; RUN: opt %loadNPMPolly -S '-passes=polly<no-default-opts>' < %s | FileCheck %s
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;
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; int jd(int *restrict A, int x, int N, int c) {
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; for (int i = 0; i < N; i++)
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; for (int j = 0; j < N; j++)
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; if (i < c)
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; x += A[i];
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; return x;
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; }
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;
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target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128"
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define i32 @jd(ptr noalias %A, i32 %x, i32 %N, i32 %c) {
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entry:
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; CHECK-LABEL: entry:
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; CHECK-DAG: %x.addr.2.s2a = alloca i32
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; CHECK-DAG: %x.addr.2.phiops = alloca i32
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; CHECK-DAG: %x.addr.1.s2a = alloca i32
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; CHECK-DAG: %x.addr.1.phiops = alloca i32
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; CHECK-DAG: %x.addr.0.s2a = alloca i32
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; CHECK-DAG: %x.addr.0.phiops = alloca i32
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%tmp = sext i32 %N to i64
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%tmp1 = sext i32 %c to i64
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br label %for.cond
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; CHECK-LABEL: polly.merge_new_and_old:
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; CHECK: %x.addr.0.merge = phi i32 [ %x.addr.0.final_reload, %polly.exiting ], [ %x.addr.0, %for.cond ]
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; CHECK: ret i32 %x.addr.0.merge
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; CHECK-LABEL: polly.start:
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; CHECK-NEXT: store i32 %x, ptr %x.addr.0.phiops
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; CHECK-NEXT: sext
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; CHECK-LABEL: polly.merge{{[a-z_0-9]*}}:
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; CHECK: %x.addr.0.final_reload = load i32, ptr %x.addr.0.s2a
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for.cond: ; preds = %for.inc5, %entry
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; CHECK-LABEL: polly.stmt.for.cond{{[0-9]*}}:
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; CHECK: %x.addr.0.phiops.reload[[R1:[0-9]*]] = load i32, ptr %x.addr.0.phiops
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; CHECK: store i32 %x.addr.0.phiops.reload[[R1]], ptr %x.addr.0.s2a
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%indvars.iv = phi i64 [ %indvars.iv.next, %for.inc5 ], [ 0, %entry ]
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%x.addr.0 = phi i32 [ %x, %entry ], [ %x.addr.1, %for.inc5 ]
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%cmp = icmp slt i64 %indvars.iv, %tmp
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br i1 %cmp, label %for.body, label %for.end7
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for.body: ; preds = %for.cond
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; CHECK-LABEL: polly.stmt.for.body:
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; CHECK: %x.addr.0.s2a.reload[[R2:[0-9]*]] = load i32, ptr %x.addr.0.s2a
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; CHECK: store i32 %x.addr.0.s2a.reload[[R2]], ptr %x.addr.1.phiops
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br label %for.cond1
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for.inc5: ; preds = %for.end
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; CHECK-LABEL: polly.stmt.for.inc5:
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; CHECK: %x.addr.1.s2a.reload[[R5:[0-9]*]] = load i32, ptr %x.addr.1.s2a
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; CHECK: store i32 %x.addr.1.s2a.reload[[R5]], ptr %x.addr.0.phiops
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%indvars.iv.next = add nuw nsw i64 %indvars.iv, 1
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br label %for.cond
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for.cond1: ; preds = %for.inc, %for.body
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; CHECK-LABEL: polly.stmt.for.cond1:
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; CHECK: %x.addr.1.phiops.reload = load i32, ptr %x.addr.1.phiops
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; CHECK: store i32 %x.addr.1.phiops.reload, ptr %x.addr.1.s2a
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%x.addr.1 = phi i32 [ %x.addr.0, %for.body ], [ %x.addr.2, %for.inc ]
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%j.0 = phi i32 [ 0, %for.body ], [ %inc, %for.inc ]
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%exitcond = icmp ne i32 %j.0, %N
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br i1 %exitcond, label %for.body3, label %for.end
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for.body3: ; preds = %for.cond1
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; CHECK-LABEL: polly.stmt.for.body3:
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; CHECK: %x.addr.1.s2a.reload = load i32, ptr %x.addr.1.s2a
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; CHECK: store i32 %x.addr.1.s2a.reload, ptr %x.addr.2.phiops
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%cmp4 = icmp slt i64 %indvars.iv, %tmp1
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br i1 %cmp4, label %if.then, label %if.end
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if.end: ; preds = %if.then, %for.body3
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; CHECK-LABEL: polly.stmt.if.end:
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; CHECK: %x.addr.2.phiops.reload = load i32, ptr %x.addr.2.phiops
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; CHECK: store i32 %x.addr.2.phiops.reload, ptr %x.addr.2.s2a
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%x.addr.2 = phi i32 [ %add, %if.then ], [ %x.addr.1, %for.body3 ]
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br label %for.inc
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for.inc: ; preds = %if.end
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; CHECK-LABEL: polly.stmt.for.inc:
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; CHECK: %x.addr.2.s2a.reload[[R3:[0-9]*]] = load i32, ptr %x.addr.2.s2a
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; CHECK: store i32 %x.addr.2.s2a.reload[[R3]], ptr %x.addr.1.phiops
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%inc = add nsw i32 %j.0, 1
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br label %for.cond1
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if.then: ; preds = %for.body3
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; CHECK-LABEL: polly.stmt.if.then:
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; CHECK: %x.addr.1.s2a.reload[[R5:[0-9]*]] = load i32, ptr %x.addr.1.s2a
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; CHECK: %p_add = add nsw i32 %x.addr.1.s2a.reload[[R5]], %tmp2_p_scalar_
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; CHECK: store i32 %p_add, ptr %x.addr.2.phiops
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%arrayidx = getelementptr inbounds i32, ptr %A, i64 %indvars.iv
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%tmp2 = load i32, ptr %arrayidx, align 4
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%add = add nsw i32 %x.addr.1, %tmp2
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br label %if.end
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for.end: ; preds = %for.cond1
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br label %for.inc5
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for.end7: ; preds = %for.cond
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ret i32 %x.addr.0
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}
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