Carl Ritson 2781f3003b [AMDGPU] Pre-commit test for D85872

2020-08-13 13:07:27 +09:00

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AArch64

[SVE][VLS] Don't combine logical AND.

2020-08-12 20:00:07 +01:00

AMDGPU

[AMDGPU] Pre-commit test for D85872

2020-08-13 13:07:27 +09:00

ARC

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ARM

[ARM] Unrestrict Armv8-a IT when at minsize

2020-08-10 14:59:53 +01:00

AVR

[AVR] Rewrite the function calling convention.

2020-06-23 21:36:18 +12:00

BPF

BPF: add a SimplifyCFG IR pass during generic Scalar/IPO optimization

2020-08-06 13:16:00 -07:00

Generic

[llc] (almost) remove --print-machineinstrs

2020-07-20 10:43:28 -07:00

Hexagon

[Hexagon] Use InstSimplify instead of ConstantProp

2020-08-04 15:42:39 -07:00

Inputs

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Lanai

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Mips

[llvm-readobj] Update tests because of changes in llvm-readobj behavior

2020-07-20 10:39:04 +01:00

MIR

AMDGPU: Serialize MFI spill fields

2020-07-28 20:01:57 -04:00

MSP430

[MSP430] Declare comparison LibCalls as returning i16 instead of i32

2020-06-30 11:04:22 +03:00

NVPTX

[NVPTX] Fix for NVPTX module asm regression

2020-06-24 11:17:09 -07:00

PowerPC

[PowerPC] Implement Vector Shift Builtins

2020-08-12 18:26:58 -05:00

RISCV

[llvm-readobj] Update tests because of changes in llvm-readobj behavior

2020-07-20 10:39:04 +01:00

SPARC

[llvm-readobj] Update tests because of changes in llvm-readobj behavior

2020-07-20 10:39:04 +01:00

SystemZ

[LegalTypes] Move VSELECT node creation out of WidenVSELECTAndMask and push to 2 of the 3 callers.

2020-08-06 13:18:16 -07:00

Thumb

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Thumb2

[ARM] Predicated VFMA patterns

2020-08-12 18:35:01 +01:00

VE

[VE] Change to promote i32 AND/OR/XOR operations

2020-08-12 16:23:50 +09:00

WebAssembly

[WebAssembly] Fix FastISel address calculation bug

2020-08-08 15:23:11 -07:00

WinCFGuard

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WinEH

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X86

[X86][GlobalISel] Legalize G_ICMP results to s8.

2020-08-12 10:13:59 -07:00

XCore

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