9d7bb0cb40
As part of the unification of the debug format and the MIR format, always print registers as lowercase. * Only debug printing is affected. It now follows MIR. Differential Revision: https://reviews.llvm.org/D40417 llvm-svn: 319187
39 lines
1.5 KiB
LLVM
39 lines
1.5 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc < %s -mtriple=i686-apple-darwin9 -mattr=+mmx,+sse4.2 | FileCheck %s --check-prefix=X32
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; RUN: llc < %s -mtriple=x86_64-apple-darwin9 -mattr=+mmx,+sse4.2 | FileCheck %s --check-prefix=X64
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; MMX insertelement is not available; these are promoted to xmm.
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; (Without SSE they are split to two ints, and the code is much better.)
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define x86_mmx @mmx_movzl(x86_mmx %x) nounwind {
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; X32-LABEL: mmx_movzl:
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; X32: ## BB#0:
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; X32-NEXT: subl $20, %esp
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; X32-NEXT: movq %mm0, {{[0-9]+}}(%esp)
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; X32-NEXT: pmovzxdq {{.*#+}} xmm0 = mem[0],zero,mem[1],zero
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; X32-NEXT: movl $32, %eax
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; X32-NEXT: pinsrd $0, %eax, %xmm0
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; X32-NEXT: pxor %xmm1, %xmm1
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; X32-NEXT: pblendw {{.*#+}} xmm1 = xmm0[0,1],xmm1[2,3,4,5,6,7]
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; X32-NEXT: movq %xmm1, (%esp)
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; X32-NEXT: movq (%esp), %mm0
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; X32-NEXT: addl $20, %esp
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; X32-NEXT: retl
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;
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; X64-LABEL: mmx_movzl:
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; X64: ## BB#0:
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; X64-NEXT: movdq2q %xmm0, %mm0
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; X64-NEXT: movq %mm0, -{{[0-9]+}}(%rsp)
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; X64-NEXT: pmovzxdq {{.*#+}} xmm1 = mem[0],zero,mem[1],zero
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; X64-NEXT: movl $32, %eax
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; X64-NEXT: pinsrq $0, %rax, %xmm1
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; X64-NEXT: pxor %xmm0, %xmm0
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; X64-NEXT: pblendw {{.*#+}} xmm0 = xmm1[0,1],xmm0[2,3,4,5,6,7]
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; X64-NEXT: retq
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%tmp = bitcast x86_mmx %x to <2 x i32>
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%tmp3 = insertelement <2 x i32> %tmp, i32 32, i32 0
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%tmp8 = insertelement <2 x i32> %tmp3, i32 0, i32 1
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%tmp9 = bitcast <2 x i32> %tmp8 to x86_mmx
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ret x86_mmx %tmp9
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}
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