AbdallahRashed 3702733820

[SelectionDAG] Fix CLMULR/CLMULH expansion (#183537) ...

For v8i8 on AArch64, `expandCLMUL` picked the zext path (ExtVT=v8i16) since ZERO_EXTEND/SRL were legal, but CLMUL on v8i16 is not, resulting in a bit-by-bit expansion (~42 insns). Prefer the bitreverse path when CLMUL is legal on VT but not ExtVT.

v8i8 CLMULR: 42 → 4 instructions.

Fixes #182780

2026-02-27 15:16:52 +00:00

..

CMakeLists.txt

[SelectionDAG] Wire up -gen-sdnode-info TableGen backend (#125358)

2025-04-06 13:14:37 +03:00

DAGCombiner.cpp

[DAG] Move (X +/- Y) & Y --> ~X & Y fold from visitAnd to SimplifyDemandedBits (#183270)

2026-02-26 11:26:00 +00:00

FastISel.cpp

[NFC][MI] Tidy Up RegState enum use (2/2) (#177090)

2026-01-23 00:19:03 -08:00

FunctionLoweringInfo.cpp

[NFC][CodeGen] Use getAllocationSize instead of manual size computation (#178360)

2026-01-28 22:48:13 -05:00

InstrEmitter.cpp

Add SDNodeFlag::NoConvergent (#179323)

2026-02-04 10:21:45 -08:00

InstrEmitter.h

[SelectionDAG] Pass SDValue to InstrEmitter::EmitCopyFromReg. NFC (#153485)

2025-08-13 21:46:48 -07:00

LegalizeDAG.cpp

[ARM] Replace manual CLS expansion with ISD::CTLS (#178430)

2026-02-19 07:49:26 -08:00

LegalizeFloatTypes.cpp

[SelectionDAG] Emit error instead of asserting for unsupported FP_EXTEND (#182660)

2026-02-21 23:22:40 +00:00

LegalizeIntegerTypes.cpp

[ARM] Replace manual CLS expansion with ISD::CTLS (#178430)

2026-02-19 07:49:26 -08:00

LegalizeTypes.cpp

DAG: Remove TypePromoteFloat (#177427)

2026-01-26 22:02:24 +00:00

LegalizeTypes.h

[ARM] Replace manual CLS expansion with ISD::CTLS (#178430)

2026-02-19 07:49:26 -08:00

LegalizeTypesGeneric.cpp

[LLVM][DAGCombiner] Look through freeze when combining extensions of loads (#175022)

2026-01-29 12:01:43 +00:00

LegalizeVectorOps.cpp

[AArch64] Add vector expansion support for ISD::FPOW when using ArmPL (#183526)

2026-02-27 09:43:05 +00:00

LegalizeVectorTypes.cpp

[SDAG] Copy flags in convertMask when legalizing vselect/setcc (#180979)

2026-02-12 08:38:37 +00:00

MatchContext.h

…

ResourcePriorityQueue.cpp

[llvm] Support building with c++23 (#154372)

2025-08-29 12:52:07 +00:00

ScheduleDAGFast.cpp

[CodeGen] Use range-based for loops (NFC) (#138488)

2025-05-05 10:08:49 -07:00

ScheduleDAGRRList.cpp

CodeGen: Remove TRI argument from getRegClass (#158225)

2025-11-10 15:43:55 -08:00

ScheduleDAGSDNodes.cpp

DAG: Remove TargetLowering::checkForPhysRegDependency (#161787)

2025-10-03 15:58:51 +00:00

ScheduleDAGSDNodes.h

…

ScheduleDAGVLIW.cpp

…

SDNodeDbgValue.h

[llvm] Use llvm::copy (NFC) (#137470)

2025-04-26 15:50:38 -07:00

SDNodeInfo.cpp

[SelectionDAG] Verify SDTCisVT and SDTCVecEltisVT constraints (#150125)

2025-11-16 18:26:03 +03:00

SelectionDAG.cpp

[PowerPC] using milicode call for memccpy instead of lib call (#182563)

2026-02-26 13:09:22 -05:00

SelectionDAGAddressAnalysis.cpp

[CodeGen] Remove handling for lifetime.start/end on non-alloca (#149838)

2025-07-22 09:44:59 +02:00

SelectionDAGBuilder.cpp

[PowerPC] using milicode call for memccpy instead of lib call (#182563)

2026-02-26 13:09:22 -05:00

SelectionDAGBuilder.h

[PowerPC] using milicode call for memccpy instead of lib call (#182563)

2026-02-26 13:09:22 -05:00

SelectionDAGDumper.cpp

Add llvm.cond.loop intrinsic.

2026-02-06 17:11:15 -08:00

SelectionDAGISel.cpp

[TableGen] Add OPC_EmitIntegerByHwMode0 and OPC_CheckChildXTypeByHwMode0. NFC (#182686)

2026-02-21 23:03:56 -08:00

SelectionDAGPrinter.cpp

…

SelectionDAGTargetInfo.cpp

[SelectionDAG] Wire up -gen-sdnode-info TableGen backend (#125358)

2025-04-06 13:14:37 +03:00

StatepointLowering.cpp

DAG: Get libcall info from LibcallLowering in more places (#176836)

2026-01-20 12:47:22 +01:00

StatepointLowering.h

…

TargetLowering.cpp

[SelectionDAG] Fix CLMULR/CLMULH expansion (#183537)

2026-02-27 15:16:52 +00:00