966a4618b8
This change extends a sign-bit reduction fold introduced earlier. Prior to it, we only supported LSHR isntructions for sign-bits extraction. Similar logic can be applied to ASHR and the fold can be generalized. ## Alive2 proofs | Reduction | == 0 | == -1 / -N | slt 0 | sgt -1 / -N | |-----------|------|------------|-------|-------------| | or | [proof](https://alive2.llvm.org/ce/z/DaSMPt) | [proof](https://alive2.llvm.org/ce/z/wzR48R) | [proof](https://alive2.llvm.org/ce/z/rfyr_7) | [proof](https://alive2.llvm.org/ce/z/MTFFe5) | | and | [proof](https://alive2.llvm.org/ce/z/PmmpbX) | [proof](https://alive2.llvm.org/ce/z/7_9hSn) | [proof](https://alive2.llvm.org/ce/z/wudWY3) | [proof](https://alive2.llvm.org/ce/z/QZ33KB) | | umax | [proof](https://alive2.llvm.org/ce/z/gQGnDc) | [proof](https://alive2.llvm.org/ce/z/dMsoQF) | [proof](https://alive2.llvm.org/ce/z/QwFbae) | [proof](https://alive2.llvm.org/ce/z/3dbmy6) | | umin | [proof](https://alive2.llvm.org/ce/z/Z2pZUQ) | [proof](https://alive2.llvm.org/ce/z/6FQgGR) | [proof](https://alive2.llvm.org/ce/z/95-em6) | [proof](https://alive2.llvm.org/ce/z/PW7c-m) | | add | [proof](https://alive2.llvm.org/ce/z/FVhuhj) | [proof](https://alive2.llvm.org/ce/z/h1B9jQ) | [proof](https://alive2.llvm.org/ce/z/DmiYRr) | [proof](https://alive2.llvm.org/ce/z/P4WDN5) |