28d7880618
Add inital implementations of these TTI methods for SIMD types. For casts, The costing covers the free extensions provided by extmul_low as well as extend_low. For memory operations we consider the use of load32_zero and load64_zero, as well as full width v128 loads.
265 lines
8.6 KiB
C++
265 lines
8.6 KiB
C++
//===-- WebAssemblyTargetTransformInfo.cpp - WebAssembly-specific TTI -----===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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///
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/// \file
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/// This file defines the WebAssembly-specific TargetTransformInfo
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/// implementation.
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///
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//===----------------------------------------------------------------------===//
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#include "WebAssemblyTargetTransformInfo.h"
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#include "llvm/CodeGen/CostTable.h"
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using namespace llvm;
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#define DEBUG_TYPE "wasmtti"
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TargetTransformInfo::PopcntSupportKind
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WebAssemblyTTIImpl::getPopcntSupport(unsigned TyWidth) const {
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assert(isPowerOf2_32(TyWidth) && "Ty width must be power of 2");
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return TargetTransformInfo::PSK_FastHardware;
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}
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unsigned WebAssemblyTTIImpl::getNumberOfRegisters(unsigned ClassID) const {
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unsigned Result = BaseT::getNumberOfRegisters(ClassID);
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// For SIMD, use at least 16 registers, as a rough guess.
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bool Vector = (ClassID == 1);
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if (Vector)
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Result = std::max(Result, 16u);
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return Result;
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}
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TypeSize WebAssemblyTTIImpl::getRegisterBitWidth(
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TargetTransformInfo::RegisterKind K) const {
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switch (K) {
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case TargetTransformInfo::RGK_Scalar:
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return TypeSize::getFixed(64);
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case TargetTransformInfo::RGK_FixedWidthVector:
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return TypeSize::getFixed(getST()->hasSIMD128() ? 128 : 64);
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case TargetTransformInfo::RGK_ScalableVector:
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return TypeSize::getScalable(0);
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}
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llvm_unreachable("Unsupported register kind");
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}
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InstructionCost WebAssemblyTTIImpl::getArithmeticInstrCost(
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unsigned Opcode, Type *Ty, TTI::TargetCostKind CostKind,
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TTI::OperandValueInfo Op1Info, TTI::OperandValueInfo Op2Info,
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ArrayRef<const Value *> Args, const Instruction *CxtI) {
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InstructionCost Cost =
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BasicTTIImplBase<WebAssemblyTTIImpl>::getArithmeticInstrCost(
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Opcode, Ty, CostKind, Op1Info, Op2Info);
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if (auto *VTy = dyn_cast<VectorType>(Ty)) {
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switch (Opcode) {
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case Instruction::LShr:
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case Instruction::AShr:
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case Instruction::Shl:
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// SIMD128's shifts currently only accept a scalar shift count. For each
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// element, we'll need to extract, op, insert. The following is a rough
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// approximation.
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if (!Op2Info.isUniform())
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Cost =
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cast<FixedVectorType>(VTy)->getNumElements() *
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(TargetTransformInfo::TCC_Basic +
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getArithmeticInstrCost(Opcode, VTy->getElementType(), CostKind) +
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TargetTransformInfo::TCC_Basic);
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break;
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}
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}
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return Cost;
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}
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InstructionCost WebAssemblyTTIImpl::getCastInstrCost(
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unsigned Opcode, Type *Dst, Type *Src, TTI::CastContextHint CCH,
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TTI::TargetCostKind CostKind, const Instruction *I) {
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int ISD = TLI->InstructionOpcodeToISD(Opcode);
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auto SrcTy = TLI->getValueType(DL, Src);
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auto DstTy = TLI->getValueType(DL, Dst);
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if (!SrcTy.isSimple() || !DstTy.isSimple()) {
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return BaseT::getCastInstrCost(Opcode, Dst, Src, CCH, CostKind, I);
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}
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if (!ST->hasSIMD128()) {
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return BaseT::getCastInstrCost(Opcode, Dst, Src, CCH, CostKind, I);
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}
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auto DstVT = DstTy.getSimpleVT();
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auto SrcVT = SrcTy.getSimpleVT();
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if (I && I->hasOneUser()) {
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auto *SingleUser = cast<Instruction>(*I->user_begin());
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int UserISD = TLI->InstructionOpcodeToISD(SingleUser->getOpcode());
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// extmul_low support
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if (UserISD == ISD::MUL &&
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(ISD == ISD::ZERO_EXTEND || ISD == ISD::SIGN_EXTEND)) {
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// Free low extensions.
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if ((SrcVT == MVT::v8i8 && DstVT == MVT::v8i16) ||
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(SrcVT == MVT::v4i16 && DstVT == MVT::v4i32) ||
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(SrcVT == MVT::v2i32 && DstVT == MVT::v2i64)) {
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return 0;
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}
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// Will require an additional extlow operation for the intermediate
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// i16/i32 value.
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if ((SrcVT == MVT::v4i8 && DstVT == MVT::v4i32) ||
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(SrcVT == MVT::v2i16 && DstVT == MVT::v2i64)) {
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return 1;
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}
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}
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}
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// extend_low
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static constexpr TypeConversionCostTblEntry ConversionTbl[] = {
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{ISD::SIGN_EXTEND, MVT::v2i64, MVT::v2i32, 1},
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{ISD::ZERO_EXTEND, MVT::v2i64, MVT::v2i32, 1},
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{ISD::SIGN_EXTEND, MVT::v4i32, MVT::v4i16, 1},
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{ISD::ZERO_EXTEND, MVT::v4i32, MVT::v4i16, 1},
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{ISD::SIGN_EXTEND, MVT::v8i16, MVT::v8i8, 1},
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{ISD::ZERO_EXTEND, MVT::v8i16, MVT::v8i8, 1},
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{ISD::SIGN_EXTEND, MVT::v2i64, MVT::v2i16, 2},
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{ISD::ZERO_EXTEND, MVT::v2i64, MVT::v2i16, 2},
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{ISD::SIGN_EXTEND, MVT::v4i32, MVT::v4i8, 2},
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{ISD::ZERO_EXTEND, MVT::v4i32, MVT::v4i8, 2},
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};
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if (const auto *Entry =
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ConvertCostTableLookup(ConversionTbl, ISD, DstVT, SrcVT)) {
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return Entry->Cost;
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}
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return BaseT::getCastInstrCost(Opcode, Dst, Src, CCH, CostKind, I);
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}
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InstructionCost WebAssemblyTTIImpl::getMemoryOpCost(
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unsigned Opcode, Type *Ty, MaybeAlign Alignment, unsigned AddressSpace,
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TTI::TargetCostKind CostKind, TTI::OperandValueInfo OpInfo,
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const Instruction *I) {
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if (!ST->hasSIMD128() || !isa<FixedVectorType>(Ty)) {
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return BaseT::getMemoryOpCost(Opcode, Ty, Alignment, AddressSpace,
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CostKind);
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}
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int ISD = TLI->InstructionOpcodeToISD(Opcode);
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if (ISD != ISD::LOAD) {
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return BaseT::getMemoryOpCost(Opcode, Ty, Alignment, AddressSpace,
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CostKind);
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}
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EVT VT = TLI->getValueType(DL, Ty, true);
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// Type legalization can't handle structs
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if (VT == MVT::Other)
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return BaseT::getMemoryOpCost(Opcode, Ty, Alignment, AddressSpace,
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CostKind);
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auto LT = getTypeLegalizationCost(Ty);
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if (!LT.first.isValid())
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return InstructionCost::getInvalid();
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// 128-bit loads are a single instruction. 32-bit and 64-bit vector loads can
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// be lowered to load32_zero and load64_zero respectively. Assume SIMD loads
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// are twice as expensive as scalar.
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unsigned width = VT.getSizeInBits();
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switch (width) {
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default:
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break;
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case 32:
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case 64:
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case 128:
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return 2;
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}
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return BaseT::getMemoryOpCost(Opcode, Ty, Alignment, AddressSpace, CostKind);
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}
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InstructionCost
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WebAssemblyTTIImpl::getVectorInstrCost(unsigned Opcode, Type *Val,
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TTI::TargetCostKind CostKind,
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unsigned Index, Value *Op0, Value *Op1) {
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InstructionCost Cost = BasicTTIImplBase::getVectorInstrCost(
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Opcode, Val, CostKind, Index, Op0, Op1);
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// SIMD128's insert/extract currently only take constant indices.
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if (Index == -1u)
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return Cost + 25 * TargetTransformInfo::TCC_Expensive;
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return Cost;
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}
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TTI::ReductionShuffle WebAssemblyTTIImpl::getPreferredExpandedReductionShuffle(
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const IntrinsicInst *II) const {
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switch (II->getIntrinsicID()) {
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default:
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break;
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case Intrinsic::vector_reduce_fadd:
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return TTI::ReductionShuffle::Pairwise;
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}
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return TTI::ReductionShuffle::SplitHalf;
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}
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void WebAssemblyTTIImpl::getUnrollingPreferences(
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Loop *L, ScalarEvolution &SE, TTI::UnrollingPreferences &UP,
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OptimizationRemarkEmitter *ORE) const {
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// Scan the loop: don't unroll loops with calls. This is a standard approach
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// for most (all?) targets.
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for (BasicBlock *BB : L->blocks())
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for (Instruction &I : *BB)
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if (isa<CallInst>(I) || isa<InvokeInst>(I))
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if (const Function *F = cast<CallBase>(I).getCalledFunction())
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if (isLoweredToCall(F))
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return;
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// The chosen threshold is within the range of 'LoopMicroOpBufferSize' of
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// the various microarchitectures that use the BasicTTI implementation and
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// has been selected through heuristics across multiple cores and runtimes.
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UP.Partial = UP.Runtime = UP.UpperBound = true;
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UP.PartialThreshold = 30;
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// Avoid unrolling when optimizing for size.
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UP.OptSizeThreshold = 0;
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UP.PartialOptSizeThreshold = 0;
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// Set number of instructions optimized when "back edge"
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// becomes "fall through" to default value of 2.
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UP.BEInsns = 2;
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}
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bool WebAssemblyTTIImpl::supportsTailCalls() const {
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return getST()->hasTailCall();
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}
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bool WebAssemblyTTIImpl::isProfitableToSinkOperands(
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Instruction *I, SmallVectorImpl<Use *> &Ops) const {
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using namespace llvm::PatternMatch;
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if (!I->getType()->isVectorTy() || !I->isShift())
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return false;
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Value *V = I->getOperand(1);
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// We dont need to sink constant splat.
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if (dyn_cast<Constant>(V))
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return false;
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if (match(V, m_Shuffle(m_InsertElt(m_Value(), m_Value(), m_ZeroInt()),
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m_Value(), m_ZeroMask()))) {
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// Sink insert
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Ops.push_back(&cast<Instruction>(V)->getOperandUse(0));
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// Sink shuffle
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Ops.push_back(&I->getOperandUse(1));
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return true;
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}
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return false;
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}
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