Sam Tebbs 8be3fc0f5c [AArch64] Disallow vscale x 1 partial reductions (#125252) ...

We don't want to allow partial reductions resulting in a vscale x 1 type
as we can't lower it in the backend.

(cherry picked from commit c7995a6905f2320f280013454676f992a8c6f89f)

2025-02-05 14:37:39 +00:00

..

AsmParser

[Build Attributes] Standardize names according to convention. (#124556)

2025-01-28 09:53:45 +00:00

Disassembler

[AArch64] Remove unused includes (NFC) (#115685)

2024-11-11 07:35:08 -08:00

GISel

[AArch64][GISel] Use Register instead of MCRegister for markPhysRegUsed in CallLowering. (#122853)

2025-01-16 07:01:01 -08:00

MCTargetDesc

[Build Attributes] Standardize names according to convention. (#124556)

2025-01-28 09:53:45 +00:00

TargetInfo

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Utils

[AArch64] Fold swapped sub/SUBS conditions (#121412)

2025-01-18 12:12:51 +00:00

AArch64.h

[MTE] Apply alignment / size in AsmPrinter rather than IR (#111918)

2024-12-17 00:47:02 -08:00

AArch64.td

[NFC][AArch64] Adjust predicate names to be more consistent (#123172)

2025-01-16 19:36:28 +00:00

AArch64A53Fix835769.cpp

[AArch64] Remove unused includes (NFC) (#115685)

2024-11-11 07:35:08 -08:00

AArch64A57FPLoadBalancing.cpp

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AArch64AdvSIMDScalarPass.cpp

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AArch64Arm64ECCallLowering.cpp

[IR] Replace of PointerType::get(Type) with opaque version (NFC) (#123617)

2025-01-21 00:32:56 +09:00

AArch64AsmPrinter.cpp

[Build Attributes] Standardize names according to convention. (#124556)

2025-01-28 09:53:45 +00:00

AArch64BranchTargets.cpp

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AArch64CallingConvention.cpp

[CallingConv] Return ArrayRef from AllocateRegBlock() (NFC) (#124120)

2025-01-23 16:33:49 +01:00

AArch64CallingConvention.h

[AArch64] Support preserve_none calling convention (#91046)

2024-06-03 18:42:08 -04:00

AArch64CallingConvention.td

[AArch64] Basic SVE PCS support for handling scalable vectors on Darwin.

2024-08-20 17:10:51 -07:00

AArch64CleanupLocalDynamicTLSPass.cpp

[aarch64][win] Update Called Globals info when updating Call Site info (#122762)

2025-01-13 14:00:31 -08:00

AArch64CollectLOH.cpp

[CodeGen] Use MCRegister instead of MCPhysReg in RegisterMaskPair. NFC (#123688)

2025-01-21 07:04:35 -08:00

AArch64Combine.td

[AArch64][GlobalISel] Full reverse shuffles. (#119083)

2024-12-29 15:56:12 +00:00

AArch64CompressJumpTables.cpp

[AArch64] Remove unused includes (NFC) (#115685)

2024-11-11 07:35:08 -08:00

AArch64CondBrTuning.cpp

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AArch64ConditionalCompares.cpp

[CodeGen][NewPM] Port machine trace metrics analysis to new pass manager. (#108507)

2024-10-16 13:19:55 +05:30

AArch64ConditionOptimizer.cpp

[CodeGen][NewPM] Split MachineDominatorTree into a concrete analysis result (#94571)

2024-06-11 21:27:14 +08:00

AArch64DeadRegisterDefinitionsPass.cpp

[AArch64] Remove unused includes (NFC) (#115685)

2024-11-11 07:35:08 -08:00

AArch64ExpandImm.cpp

[AArch64] Optimize MOV to ORR when load symmetric constants (#86249)

2024-05-20 09:57:50 +01:00

AArch64ExpandImm.h

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AArch64ExpandPseudoInsts.cpp

[aarch64][win] Update Called Globals info when updating Call Site info (#122762)

2025-01-13 14:00:31 -08:00

AArch64FalkorHWPFFix.cpp

[CodeGen][NewPM] Port machine-loops to new pass manager (#97793)

2024-07-09 09:11:18 +08:00

AArch64FastISel.cpp

[AArch64] SME implementation for agnostic-ZA functions (#120150)

2024-12-23 19:10:21 +00:00

AArch64Features.td

[AArch64] Avoid generating LDAPUR on certain cores (#124274)

2025-01-27 13:12:11 +00:00

AArch64FMV.td

[FMV][AArch64] Remove features predres and ls64. (#124266)

2025-01-24 17:22:27 +00:00

AArch64FrameLowering.cpp

[AArch64][WinCFI] Fix a crash due to missing seh directives (#123993)

2025-01-24 14:01:41 -08:00

AArch64FrameLowering.h

[AArch64] Fix a corner case with large stack allocation (#122038)

2025-01-18 22:09:25 -08:00

AArch64GenRegisterBankInfo.def

[GlobalISel][AArch64] Legalize G_ADD, G_SUB, G_AND, G_OR, and G_XOR for SVE (#110561)

2024-10-27 23:14:07 +01:00

AArch64InstrAtomics.td

[AArch64] Avoid generating LDAPUR on certain cores (#124274)

2025-01-27 13:12:11 +00:00

AArch64InstrFormats.td

[AArch64] Implement NEON FP8 intrinsics for fused multiply-add (#123615)

2025-01-28 00:38:44 +00:00

AArch64InstrGISel.td

DAG: Replace bitwidth with type in suffix in atomic tablegen ops (#94845)

2024-06-13 11:52:22 +02:00

AArch64InstrInfo.cpp

[llvm][CodeGen] Fix the issue caused by live interval checking in window scheduler (#123184)

2025-01-23 09:39:03 +08:00

AArch64InstrInfo.h

[llvm] Pass MachineInstr flags to storeRegToStackSlot/loadRegFromStackSlot (NFC) (#120622)

2025-01-22 13:36:39 +05:30

AArch64InstrInfo.td

[AArch64] PAUTH_PROLOGUE should not be duplicated with PAuthLR (#124775)

2025-01-31 17:55:58 -08:00

AArch64ISelDAGToDAG.cpp

[AArch64] Allow register offset addressing mode for prefetch (#124534)

2025-01-28 09:16:40 +00:00

AArch64ISelLowering.cpp

Reapply "[AArch64] Combine and and lsl into ubfiz" (#123356) (#124576)

2025-01-28 11:27:34 +00:00

AArch64ISelLowering.h

[IA] Generalize the support for power-of-two (de)interleave intrinsics (#123863)

2025-01-23 15:27:51 -08:00

AArch64LoadStoreOptimizer.cpp

[AArch64] Fix LDR/STR folding causing memtag failures (#118821)

2024-12-06 13:07:37 +00:00

AArch64LowerHomogeneousPrologEpilog.cpp

[AArch64] Do not mark homogeneous prolog/epilog functions optnone (#117959)

2024-11-28 00:11:05 -08:00

AArch64MachineFunctionInfo.cpp

[PAC][CodeGen][ELF][AArch64] Support signed GOT (#113811)

2024-11-01 12:21:10 +03:00

AArch64MachineFunctionInfo.h

[AArch64] SME implementation for agnostic-ZA functions (#120150)

2024-12-23 19:10:21 +00:00

AArch64MachineScheduler.cpp

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AArch64MachineScheduler.h

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AArch64MacroFusion.cpp

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AArch64MacroFusion.h

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AArch64MCInstLower.cpp

[PAC][MC][ELF][AArch64] Support signed TLSDESC (#120010)

2024-12-19 12:40:33 +03:00

AArch64MCInstLower.h

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AArch64MIPeepholeOpt.cpp

Fix typo "intead"

2024-11-21 14:48:38 +00:00

AArch64PBQPRegAlloc.cpp

[NFC] Remove some unnecessary semicolons

2024-12-16 08:48:57 +00:00

AArch64PBQPRegAlloc.h

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AArch64PerfectShuffle.h

[AArch64][GlobalISel] Common some shuffle mask functions.

2024-05-06 18:37:04 +01:00

AArch64PfmCounters.td

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AArch64PointerAuth.cpp

[AArch64] Correct position of CFI Instruction for Pointer Authentication (#121559)

2025-01-06 09:39:50 +00:00

AArch64PointerAuth.h

[AArch64][PAC] Move emission of LR checks in tail calls to AsmPrinter (#110705)

2024-11-12 18:27:19 +03:00

AArch64PostCoalescerPass.cpp

[AArch64] Remove unused includes (NFC) (#115685)

2024-11-11 07:35:08 -08:00

AArch64Processors.td

[AArch64] Avoid generating LDAPUR on certain cores (#124274)

2025-01-27 13:12:11 +00:00

AArch64PromoteConstant.cpp

[AArch64] Remove unused includes (NFC) (#115685)

2024-11-11 07:35:08 -08:00

AArch64RedundantCopyElimination.cpp

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AArch64RegisterBanks.td

[AArch64][GISel] Support SVE with 128-bit min-size for G_LOAD and G_STORE (#92130)

2024-05-30 09:10:43 +01:00

AArch64RegisterInfo.cpp

[AArch64][SME2] Extend getRegAllocationHints for ZPRStridedOrContiguousReg (#119865)

2024-12-19 09:40:13 +00:00

AArch64RegisterInfo.h

[AArch64][SME2] Improve register allocation of multi-vector SME intrinsics (#116399)

2024-12-12 10:00:24 +00:00

AArch64RegisterInfo.td

[AArch64] Verify consecutive vector registers in tbl, tbx (#120262)

2024-12-20 20:08:24 +02:00

AArch64SchedA53.td

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AArch64SchedA55.td

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AArch64SchedA57.td

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AArch64SchedA57WriteRes.td

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AArch64SchedA64FX.td

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AArch64SchedA510.td

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AArch64SchedAmpere1.td

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AArch64SchedAmpere1B.td

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AArch64SchedCyclone.td

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AArch64SchedExynosM3.td

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AArch64SchedExynosM4.td

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AArch64SchedExynosM5.td

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AArch64SchedFalkor.td

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AArch64SchedFalkorDetails.td

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AArch64SchedKryo.td

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AArch64SchedKryoDetails.td

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AArch64SchedNeoverseN1.td

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AArch64SchedNeoverseN2.td

[AArch64][machine-scheduler][Neoverse-N2] fdiv is blocking (#119206)

2025-01-06 21:57:15 +00:00

AArch64SchedNeoverseN3.td

[AArch64] Initial sched model for Neoverse N3 (#106371)

2024-09-19 19:22:24 +01:00

AArch64SchedNeoverseV1.td

[AArch64] Fix scheduling information for arithmetic and logical instructions. (#113542)

2024-12-04 09:30:44 +00:00

AArch64SchedNeoverseV2.td

[AArch64] Fix scheduling information for arithmetic and logical instructions. (#113542)

2024-12-04 09:30:44 +00:00

AArch64SchedOryon.td

[AArch64] Add support for Qualcomm Oryon processor (#91022)

2024-06-06 07:27:50 -07:00

AArch64SchedPredExynos.td

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AArch64SchedPredicates.td

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AArch64SchedPredNeoverse.td

[AArch64] Fix scheduling model issue #96394 (#97047)

2024-07-01 11:34:23 +01:00

AArch64SchedThunderX2T99.td

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AArch64SchedThunderX3T110.td

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AArch64SchedThunderX.td

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AArch64SchedTSV110.td

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AArch64Schedule.td

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AArch64SelectionDAGInfo.cpp

[SelectionDAG] Virtualize isTargetStrictFPOpcode / isTargetMemoryOpcode (#119969)

2024-12-21 05:29:51 +03:00

AArch64SelectionDAGInfo.h

[SelectionDAG] Virtualize isTargetStrictFPOpcode / isTargetMemoryOpcode (#119969)

2024-12-21 05:29:51 +03:00

AArch64SIMDInstrOpt.cpp

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AArch64SLSHardening.cpp

[aarch64][win] Update Called Globals info when updating Call Site info (#122762)

2025-01-13 14:00:31 -08:00

AArch64SMEInstrInfo.td

[NFC][AArch64] Adjust predicate names to be more consistent (#123172)

2025-01-16 19:36:28 +00:00

AArch64SpeculationHardening.cpp

[AArch64] Remove unused includes (NFC) (#115685)

2024-11-11 07:35:08 -08:00

AArch64StackTagging.cpp

[AArch64] Remove unused includes (NFC) (#115685)

2024-11-11 07:35:08 -08:00

AArch64StackTaggingPreRA.cpp

[AArch64] Remove unused includes (NFC) (#115685)

2024-11-11 07:35:08 -08:00

AArch64StorePairSuppress.cpp

[CodeGen][NewPM] Port machine trace metrics analysis to new pass manager. (#108507)

2024-10-16 13:19:55 +05:30

AArch64Subtarget.cpp

[AArch64] Set the default streaming hazard size to 1024 for +sme,+sve (#123753)

2025-01-22 09:08:17 +00:00

AArch64Subtarget.h

[AArch64] Set the default streaming hazard size to 1024 for +sme,+sve (#123753)

2025-01-22 09:08:17 +00:00

AArch64SVEInstrInfo.td

[AArch64] Generate zeroing forms of certain SVE2.2 instructions (11/11) (#116837)

2025-01-27 18:12:00 +00:00

AArch64SystemOperands.td

[AArch64] Add DC CIGDPAPA and DC CIPAPA instructions (#122718)

2025-01-14 08:35:36 +00:00

AArch64TargetMachine.cpp

[MTE] Apply alignment / size in AsmPrinter rather than IR (#111918)

2024-12-17 00:47:02 -08:00

AArch64TargetMachine.h

Overhaul the TargetMachine and LLVMTargetMachine Classes (#111234)

2024-11-14 13:30:05 -08:00

AArch64TargetObjectFile.cpp

[PAC][ELF][AArch64] Support signed personality function pointer (#119361)

2024-12-16 10:24:09 +03:00

AArch64TargetObjectFile.h

[PAC][ELF][AArch64] Support signed personality function pointer (#119361)

2024-12-16 10:24:09 +03:00

AArch64TargetTransformInfo.cpp

[AArch64] Disallow vscale x 1 partial reductions (#125252)

2025-02-05 14:37:39 +00:00

AArch64TargetTransformInfo.h

[AArch64][NFC] Move getPartialReductionCost into cpp file (#123370)

2025-01-20 14:07:03 +00:00

CMakeLists.txt

[MTE] Apply alignment / size in AsmPrinter rather than IR (#111918)

2024-12-17 00:47:02 -08:00

SMEABIPass.cpp

[AArch64] Remove unused includes (NFC) (#115685)

2024-11-11 07:35:08 -08:00

SMEInstrFormats.td

[AArch64][SME] Change output class of FORM_TRANSPOSED_REG_TUPLE pseudos (#123755)

2025-01-24 09:47:29 +00:00

SMEPeepholeOpt.cpp

[AArch64] Remove unused includes (NFC) (#115685)

2024-11-11 07:35:08 -08:00

SVEInstrFormats.td

[AArch64] Generate zeroing forms of certain SVE2.2 instructions (11/11) (#116837)

2025-01-27 18:12:00 +00:00

SVEIntrinsicOpts.cpp

[AArch64] Remove unused includes (NFC) (#115685)

2024-11-11 07:35:08 -08:00