2946cd7010
to reflect the new license. We understand that people may be surprised that we're moving the header entirely to discuss the new license. We checked this carefully with the Foundation's lawyer and we believe this is the correct approach. Essentially, all code in the project is now made available by the LLVM project under our new license, so you will see that the license headers include that license only. Some of our contributors have contributed code under our old license, and accordingly, we have retained a copy of our old license notice in the top-level files in each project and repository. llvm-svn: 351636
400 lines
15 KiB
C++
400 lines
15 KiB
C++
//===-- WebAssemblyExplicitLocals.cpp - Make Locals Explicit --------------===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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///
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/// \file
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/// This file converts any remaining registers into WebAssembly locals.
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///
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/// After register stackification and register coloring, convert non-stackified
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/// registers into locals, inserting explicit local.get and local.set
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/// instructions.
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///
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//===----------------------------------------------------------------------===//
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#include "MCTargetDesc/WebAssemblyMCTargetDesc.h"
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#include "WebAssembly.h"
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#include "WebAssemblyMachineFunctionInfo.h"
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#include "WebAssemblySubtarget.h"
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#include "WebAssemblyUtilities.h"
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#include "llvm/CodeGen/MachineBlockFrequencyInfo.h"
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#include "llvm/CodeGen/MachineInstrBuilder.h"
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#include "llvm/CodeGen/MachineRegisterInfo.h"
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#include "llvm/CodeGen/Passes.h"
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#include "llvm/Support/Debug.h"
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#include "llvm/Support/raw_ostream.h"
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using namespace llvm;
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#define DEBUG_TYPE "wasm-explicit-locals"
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// A command-line option to disable this pass, and keep implicit locals
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// for the purpose of testing with lit/llc ONLY.
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// This produces output which is not valid WebAssembly, and is not supported
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// by assemblers/disassemblers and other MC based tools.
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static cl::opt<bool> WasmDisableExplicitLocals(
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"wasm-disable-explicit-locals", cl::Hidden,
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cl::desc("WebAssembly: output implicit locals in"
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" instruction output for test purposes only."),
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cl::init(false));
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namespace {
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class WebAssemblyExplicitLocals final : public MachineFunctionPass {
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StringRef getPassName() const override {
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return "WebAssembly Explicit Locals";
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}
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void getAnalysisUsage(AnalysisUsage &AU) const override {
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AU.setPreservesCFG();
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AU.addPreserved<MachineBlockFrequencyInfo>();
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MachineFunctionPass::getAnalysisUsage(AU);
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}
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bool runOnMachineFunction(MachineFunction &MF) override;
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public:
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static char ID; // Pass identification, replacement for typeid
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WebAssemblyExplicitLocals() : MachineFunctionPass(ID) {}
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};
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} // end anonymous namespace
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char WebAssemblyExplicitLocals::ID = 0;
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INITIALIZE_PASS(WebAssemblyExplicitLocals, DEBUG_TYPE,
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"Convert registers to WebAssembly locals", false, false)
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FunctionPass *llvm::createWebAssemblyExplicitLocals() {
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return new WebAssemblyExplicitLocals();
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}
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/// Return a local id number for the given register, assigning it a new one
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/// if it doesn't yet have one.
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static unsigned getLocalId(DenseMap<unsigned, unsigned> &Reg2Local,
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unsigned &CurLocal, unsigned Reg) {
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auto P = Reg2Local.insert(std::make_pair(Reg, CurLocal));
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if (P.second)
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++CurLocal;
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return P.first->second;
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}
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/// Get the appropriate drop opcode for the given register class.
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static unsigned getDropOpcode(const TargetRegisterClass *RC) {
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if (RC == &WebAssembly::I32RegClass)
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return WebAssembly::DROP_I32;
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if (RC == &WebAssembly::I64RegClass)
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return WebAssembly::DROP_I64;
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if (RC == &WebAssembly::F32RegClass)
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return WebAssembly::DROP_F32;
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if (RC == &WebAssembly::F64RegClass)
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return WebAssembly::DROP_F64;
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if (RC == &WebAssembly::V128RegClass)
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return WebAssembly::DROP_V128;
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if (RC == &WebAssembly::EXCEPT_REFRegClass)
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return WebAssembly::DROP_EXCEPT_REF;
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llvm_unreachable("Unexpected register class");
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}
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/// Get the appropriate local.get opcode for the given register class.
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static unsigned getGetLocalOpcode(const TargetRegisterClass *RC) {
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if (RC == &WebAssembly::I32RegClass)
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return WebAssembly::LOCAL_GET_I32;
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if (RC == &WebAssembly::I64RegClass)
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return WebAssembly::LOCAL_GET_I64;
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if (RC == &WebAssembly::F32RegClass)
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return WebAssembly::LOCAL_GET_F32;
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if (RC == &WebAssembly::F64RegClass)
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return WebAssembly::LOCAL_GET_F64;
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if (RC == &WebAssembly::V128RegClass)
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return WebAssembly::LOCAL_GET_V128;
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if (RC == &WebAssembly::EXCEPT_REFRegClass)
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return WebAssembly::LOCAL_GET_EXCEPT_REF;
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llvm_unreachable("Unexpected register class");
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}
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/// Get the appropriate local.set opcode for the given register class.
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static unsigned getSetLocalOpcode(const TargetRegisterClass *RC) {
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if (RC == &WebAssembly::I32RegClass)
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return WebAssembly::LOCAL_SET_I32;
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if (RC == &WebAssembly::I64RegClass)
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return WebAssembly::LOCAL_SET_I64;
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if (RC == &WebAssembly::F32RegClass)
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return WebAssembly::LOCAL_SET_F32;
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if (RC == &WebAssembly::F64RegClass)
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return WebAssembly::LOCAL_SET_F64;
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if (RC == &WebAssembly::V128RegClass)
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return WebAssembly::LOCAL_SET_V128;
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if (RC == &WebAssembly::EXCEPT_REFRegClass)
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return WebAssembly::LOCAL_SET_EXCEPT_REF;
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llvm_unreachable("Unexpected register class");
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}
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/// Get the appropriate local.tee opcode for the given register class.
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static unsigned getTeeLocalOpcode(const TargetRegisterClass *RC) {
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if (RC == &WebAssembly::I32RegClass)
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return WebAssembly::LOCAL_TEE_I32;
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if (RC == &WebAssembly::I64RegClass)
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return WebAssembly::LOCAL_TEE_I64;
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if (RC == &WebAssembly::F32RegClass)
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return WebAssembly::LOCAL_TEE_F32;
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if (RC == &WebAssembly::F64RegClass)
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return WebAssembly::LOCAL_TEE_F64;
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if (RC == &WebAssembly::V128RegClass)
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return WebAssembly::LOCAL_TEE_V128;
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if (RC == &WebAssembly::EXCEPT_REFRegClass)
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return WebAssembly::LOCAL_TEE_EXCEPT_REF;
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llvm_unreachable("Unexpected register class");
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}
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/// Get the type associated with the given register class.
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static MVT typeForRegClass(const TargetRegisterClass *RC) {
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if (RC == &WebAssembly::I32RegClass)
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return MVT::i32;
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if (RC == &WebAssembly::I64RegClass)
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return MVT::i64;
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if (RC == &WebAssembly::F32RegClass)
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return MVT::f32;
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if (RC == &WebAssembly::F64RegClass)
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return MVT::f64;
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if (RC == &WebAssembly::V128RegClass)
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return MVT::v16i8;
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if (RC == &WebAssembly::EXCEPT_REFRegClass)
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return MVT::ExceptRef;
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llvm_unreachable("unrecognized register class");
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}
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/// Given a MachineOperand of a stackified vreg, return the instruction at the
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/// start of the expression tree.
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static MachineInstr *findStartOfTree(MachineOperand &MO,
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MachineRegisterInfo &MRI,
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WebAssemblyFunctionInfo &MFI) {
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unsigned Reg = MO.getReg();
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assert(MFI.isVRegStackified(Reg));
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MachineInstr *Def = MRI.getVRegDef(Reg);
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// Find the first stackified use and proceed from there.
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for (MachineOperand &DefMO : Def->explicit_uses()) {
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if (!DefMO.isReg())
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continue;
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return findStartOfTree(DefMO, MRI, MFI);
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}
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// If there were no stackified uses, we've reached the start.
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return Def;
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}
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bool WebAssemblyExplicitLocals::runOnMachineFunction(MachineFunction &MF) {
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LLVM_DEBUG(dbgs() << "********** Make Locals Explicit **********\n"
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"********** Function: "
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<< MF.getName() << '\n');
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// Disable this pass if directed to do so.
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if (WasmDisableExplicitLocals)
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return false;
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bool Changed = false;
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MachineRegisterInfo &MRI = MF.getRegInfo();
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WebAssemblyFunctionInfo &MFI = *MF.getInfo<WebAssemblyFunctionInfo>();
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const auto *TII = MF.getSubtarget<WebAssemblySubtarget>().getInstrInfo();
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// Map non-stackified virtual registers to their local ids.
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DenseMap<unsigned, unsigned> Reg2Local;
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// Handle ARGUMENTS first to ensure that they get the designated numbers.
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for (MachineBasicBlock::iterator I = MF.begin()->begin(),
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E = MF.begin()->end();
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I != E;) {
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MachineInstr &MI = *I++;
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if (!WebAssembly::isArgument(MI))
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break;
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unsigned Reg = MI.getOperand(0).getReg();
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assert(!MFI.isVRegStackified(Reg));
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Reg2Local[Reg] = static_cast<unsigned>(MI.getOperand(1).getImm());
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MI.eraseFromParent();
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Changed = true;
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}
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// Start assigning local numbers after the last parameter.
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unsigned CurLocal = static_cast<unsigned>(MFI.getParams().size());
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// Precompute the set of registers that are unused, so that we can insert
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// drops to their defs.
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BitVector UseEmpty(MRI.getNumVirtRegs());
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for (unsigned I = 0, E = MRI.getNumVirtRegs(); I < E; ++I)
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UseEmpty[I] = MRI.use_empty(TargetRegisterInfo::index2VirtReg(I));
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// Visit each instruction in the function.
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for (MachineBasicBlock &MBB : MF) {
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for (MachineBasicBlock::iterator I = MBB.begin(), E = MBB.end(); I != E;) {
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MachineInstr &MI = *I++;
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assert(!WebAssembly::isArgument(MI));
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if (MI.isDebugInstr() || MI.isLabel())
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continue;
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// Replace tee instructions with local.tee. The difference is that tee
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// instructions have two defs, while local.tee instructions have one def
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// and an index of a local to write to.
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if (WebAssembly::isTee(MI)) {
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assert(MFI.isVRegStackified(MI.getOperand(0).getReg()));
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assert(!MFI.isVRegStackified(MI.getOperand(1).getReg()));
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unsigned OldReg = MI.getOperand(2).getReg();
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const TargetRegisterClass *RC = MRI.getRegClass(OldReg);
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// Stackify the input if it isn't stackified yet.
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if (!MFI.isVRegStackified(OldReg)) {
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unsigned LocalId = getLocalId(Reg2Local, CurLocal, OldReg);
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unsigned NewReg = MRI.createVirtualRegister(RC);
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unsigned Opc = getGetLocalOpcode(RC);
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BuildMI(MBB, &MI, MI.getDebugLoc(), TII->get(Opc), NewReg)
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.addImm(LocalId);
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MI.getOperand(2).setReg(NewReg);
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MFI.stackifyVReg(NewReg);
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}
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// Replace the TEE with a LOCAL_TEE.
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unsigned LocalId =
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getLocalId(Reg2Local, CurLocal, MI.getOperand(1).getReg());
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unsigned Opc = getTeeLocalOpcode(RC);
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BuildMI(MBB, &MI, MI.getDebugLoc(), TII->get(Opc),
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MI.getOperand(0).getReg())
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.addImm(LocalId)
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.addReg(MI.getOperand(2).getReg());
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MI.eraseFromParent();
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Changed = true;
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continue;
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}
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// Insert local.sets for any defs that aren't stackified yet. Currently
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// we handle at most one def.
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assert(MI.getDesc().getNumDefs() <= 1);
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if (MI.getDesc().getNumDefs() == 1) {
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unsigned OldReg = MI.getOperand(0).getReg();
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if (!MFI.isVRegStackified(OldReg)) {
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const TargetRegisterClass *RC = MRI.getRegClass(OldReg);
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unsigned NewReg = MRI.createVirtualRegister(RC);
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auto InsertPt = std::next(MachineBasicBlock::iterator(&MI));
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if (MI.getOpcode() == WebAssembly::IMPLICIT_DEF) {
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MI.eraseFromParent();
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Changed = true;
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continue;
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}
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if (UseEmpty[TargetRegisterInfo::virtReg2Index(OldReg)]) {
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unsigned Opc = getDropOpcode(RC);
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MachineInstr *Drop =
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BuildMI(MBB, InsertPt, MI.getDebugLoc(), TII->get(Opc))
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.addReg(NewReg);
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// After the drop instruction, this reg operand will not be used
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Drop->getOperand(0).setIsKill();
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} else {
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unsigned LocalId = getLocalId(Reg2Local, CurLocal, OldReg);
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unsigned Opc = getSetLocalOpcode(RC);
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BuildMI(MBB, InsertPt, MI.getDebugLoc(), TII->get(Opc))
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.addImm(LocalId)
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.addReg(NewReg);
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}
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MI.getOperand(0).setReg(NewReg);
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// This register operand of the original instruction is now being used
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// by the inserted drop or local.set instruction, so make it not dead
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// yet.
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MI.getOperand(0).setIsDead(false);
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MFI.stackifyVReg(NewReg);
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Changed = true;
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}
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}
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// Insert local.gets for any uses that aren't stackified yet.
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MachineInstr *InsertPt = &MI;
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for (MachineOperand &MO : reverse(MI.explicit_uses())) {
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if (!MO.isReg())
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continue;
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unsigned OldReg = MO.getReg();
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// Inline asm may have a def in the middle of the operands. Our contract
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// with inline asm register operands is to provide local indices as
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// immediates.
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if (MO.isDef()) {
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assert(MI.getOpcode() == TargetOpcode::INLINEASM);
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unsigned LocalId = getLocalId(Reg2Local, CurLocal, OldReg);
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// If this register operand is tied to another operand, we can't
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// change it to an immediate. Untie it first.
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MI.untieRegOperand(MI.getOperandNo(&MO));
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MO.ChangeToImmediate(LocalId);
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continue;
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}
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// If we see a stackified register, prepare to insert subsequent
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// local.gets before the start of its tree.
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if (MFI.isVRegStackified(OldReg)) {
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InsertPt = findStartOfTree(MO, MRI, MFI);
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continue;
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}
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// Our contract with inline asm register operands is to provide local
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// indices as immediates.
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if (MI.getOpcode() == TargetOpcode::INLINEASM) {
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unsigned LocalId = getLocalId(Reg2Local, CurLocal, OldReg);
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// Untie it first if this reg operand is tied to another operand.
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MI.untieRegOperand(MI.getOperandNo(&MO));
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MO.ChangeToImmediate(LocalId);
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continue;
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}
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// Insert a local.get.
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unsigned LocalId = getLocalId(Reg2Local, CurLocal, OldReg);
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const TargetRegisterClass *RC = MRI.getRegClass(OldReg);
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unsigned NewReg = MRI.createVirtualRegister(RC);
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unsigned Opc = getGetLocalOpcode(RC);
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InsertPt =
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BuildMI(MBB, InsertPt, MI.getDebugLoc(), TII->get(Opc), NewReg)
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.addImm(LocalId);
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MO.setReg(NewReg);
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MFI.stackifyVReg(NewReg);
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Changed = true;
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}
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// Coalesce and eliminate COPY instructions.
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if (WebAssembly::isCopy(MI)) {
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MRI.replaceRegWith(MI.getOperand(1).getReg(),
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MI.getOperand(0).getReg());
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MI.eraseFromParent();
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Changed = true;
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}
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}
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}
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// Define the locals.
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// TODO: Sort the locals for better compression.
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MFI.setNumLocals(CurLocal - MFI.getParams().size());
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for (unsigned I = 0, E = MRI.getNumVirtRegs(); I < E; ++I) {
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unsigned Reg = TargetRegisterInfo::index2VirtReg(I);
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auto RL = Reg2Local.find(Reg);
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if (RL == Reg2Local.end() || RL->second < MFI.getParams().size())
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continue;
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MFI.setLocal(RL->second - MFI.getParams().size(),
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typeForRegClass(MRI.getRegClass(Reg)));
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Changed = true;
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}
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#ifndef NDEBUG
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// Assert that all registers have been stackified at this point.
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for (const MachineBasicBlock &MBB : MF) {
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for (const MachineInstr &MI : MBB) {
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if (MI.isDebugInstr() || MI.isLabel())
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continue;
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for (const MachineOperand &MO : MI.explicit_operands()) {
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assert(
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(!MO.isReg() || MRI.use_empty(MO.getReg()) ||
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MFI.isVRegStackified(MO.getReg())) &&
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"WebAssemblyExplicitLocals failed to stackify a register operand");
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}
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}
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}
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#endif
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return Changed;
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}
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