fe6c9cbb24
Planning to add support for named vregs. This puts is in a conundrum since physregs are named as well. To rectify this we need to use a sigil other than '%' for physregs in MIR. We've settled on using '$' for physregs but first we must repurpose it from external symbols using it, which is what this commit is all about. We think '&' will have familiar semantics for C/C++ users. llvm-svn: 322146
61 lines
1.7 KiB
YAML
61 lines
1.7 KiB
YAML
# RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs -run-pass post-RA-hazard-rec %s -o - | FileCheck -check-prefix=GCN -check-prefix=VI %s
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# RUN: llc -march=amdgcn -mcpu=gfx900 -verify-machineinstrs -run-pass post-RA-hazard-rec %s -o - | FileCheck -check-prefix=GCN -check-prefix=GFX9 %s
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# GCN-LABEL: name: hazard_implicit_def
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# GCN: bb.0.entry:
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# GCN: %m0 = S_MOV_B32
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# GFX9: S_NOP 0
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# VI-NOT: S_NOP_0
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# GCN: V_INTERP_P1_F32
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---
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name: hazard_implicit_def
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alignment: 0
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exposesReturnsTwice: false
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legalized: false
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regBankSelected: false
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selected: false
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tracksRegLiveness: true
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registers:
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liveins:
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- { reg: '%sgpr7', virtual-reg: '' }
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- { reg: '%vgpr4', virtual-reg: '' }
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body: |
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bb.0.entry:
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liveins: %sgpr7, %vgpr4
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%m0 = S_MOV_B32 killed %sgpr7
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%vgpr5 = IMPLICIT_DEF
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%vgpr0 = V_INTERP_P1_F32 killed %vgpr4, 0, 0, implicit %m0, implicit %exec
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SI_RETURN_TO_EPILOG killed %vgpr5, killed %vgpr0
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...
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# GCN-LABEL: name: hazard_inlineasm
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# GCN: bb.0.entry:
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# GCN: %m0 = S_MOV_B32
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# GFX9: S_NOP 0
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# VI-NOT: S_NOP_0
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# GCN: V_INTERP_P1_F32
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---
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name: hazard_inlineasm
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alignment: 0
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exposesReturnsTwice: false
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legalized: false
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regBankSelected: false
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selected: false
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tracksRegLiveness: true
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registers:
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liveins:
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- { reg: '%sgpr7', virtual-reg: '' }
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- { reg: '%vgpr4', virtual-reg: '' }
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body: |
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bb.0.entry:
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liveins: %sgpr7, %vgpr4
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%m0 = S_MOV_B32 killed %sgpr7
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INLINEASM &"; no-op", 1, 327690, def %vgpr5
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%vgpr0 = V_INTERP_P1_F32 killed %vgpr4, 0, 0, implicit %m0, implicit %exec
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SI_RETURN_TO_EPILOG killed %vgpr5, killed %vgpr0
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...
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