Alex Bradbury 0715d35ed5 [RISCV] Reserve an emergency spill slot for the register scavenger when necessary ...

Although the register scavenger can often find a spare register, an emergency 
spill slot is needed to guarantee success. Reserve this slot in cases where 
the function is known to have a large stack (meaning the scavenger may be 
needed when forming stack addresses).

llvm-svn: 322269

2018-01-11 11:17:19 +00:00

..

addc-adde-sube-subc.ll

[RISCV] Enable emission of alias instructions by default

2017-12-15 09:47:01 +00:00

alloca.ll

[RISCV] Enable emission of alias instructions by default

2017-12-15 09:47:01 +00:00

alu32.ll

[RISCV] Enable emission of alias instructions by default

2017-12-15 09:47:01 +00:00

analyze-branch.ll

[RISCV] Implement support for the BranchRelaxation pass

2018-01-10 21:05:07 +00:00

bare-select.ll

[RISCV] Enable emission of alias instructions by default

2017-12-15 09:47:01 +00:00

blockaddress.ll

[RISCV] Enable emission of alias instructions by default

2017-12-15 09:47:01 +00:00

branch-relaxation.ll

[RISCV] Implement support for the BranchRelaxation pass

2018-01-10 21:05:07 +00:00

branch.ll

[RISCV] Implement branch analysis

2018-01-10 20:47:00 +00:00

bswap-ctlz-cttz-ctpop.ll

[RISCV] Implement support for the BranchRelaxation pass

2018-01-10 21:05:07 +00:00

byval.ll

[RISCV] Enable emission of alias instructions by default

2017-12-15 09:47:01 +00:00

calling-conv-sext-zext.ll

[RISCV] Enable emission of alias instructions by default

2017-12-15 09:47:01 +00:00

calling-conv.ll

[RISCV] Enable emission of alias instructions by default

2017-12-15 09:47:01 +00:00

calls.ll

[RISCV] Enable emission of alias instructions by default

2017-12-15 09:47:01 +00:00

div.ll

[RISCV] Enable emission of alias instructions by default

2017-12-15 09:47:01 +00:00

fp128.ll

[RISCV] Enable emission of alias instructions by default

2017-12-15 09:47:01 +00:00

frame.ll

[RISCV] Enable emission of alias instructions by default

2017-12-15 09:47:01 +00:00

frameaddr-returnaddr.ll

[RISCV] Add support for llvm.{frameaddress,returnaddress} intrinsics

2018-01-10 20:12:00 +00:00

i32-icmp.ll

[RISCV] Enable emission of alias instructions by default

2017-12-15 09:47:01 +00:00

imm.ll

[RISCV] Enable emission of alias instructions by default

2017-12-15 09:47:01 +00:00

indirectbr.ll

[RISCV] Enable emission of alias instructions by default

2017-12-15 09:47:01 +00:00

inline-asm.ll

[RISCV] Add basic support for inline asm constraints

2018-01-10 20:05:09 +00:00

jumptable.ll

[RISCV] Implement support for the BranchRelaxation pass

2018-01-10 21:05:07 +00:00

large-stack.ll

[RISCV] Reserve an emergency spill slot for the register scavenger when necessary

2018-01-11 11:17:19 +00:00

lit.local.cfg

…

mem.ll

[RISCV] Enable emission of alias instructions by default

2017-12-15 09:47:01 +00:00

mul.ll

[RISCV] Enable emission of alias instructions by default

2017-12-15 09:47:01 +00:00

rem.ll

[RISCV] Enable emission of alias instructions by default

2017-12-15 09:47:01 +00:00

rotl-rotr.ll

[RISCV] Enable emission of alias instructions by default

2017-12-15 09:47:01 +00:00

select-cc.ll

[RISCV] Implement branch analysis

2018-01-10 20:47:00 +00:00

sext-zext-trunc.ll

[RISCV] Enable emission of alias instructions by default

2017-12-15 09:47:01 +00:00

shifts.ll

[RISCV] Enable emission of alias instructions by default

2017-12-15 09:47:01 +00:00

vararg.ll

[RISCV] Support for varargs

2018-01-10 19:41:03 +00:00

wide-mem.ll

[RISCV] Enable emission of alias instructions by default

2017-12-15 09:47:01 +00:00