60c431022e
Summary: Add isRenamable() predicate to MachineOperand. This predicate can be used by machine passes after register allocation to determine whether it is safe to rename a given register operand. Register operands that aren't marked as renamable may be required to be assigned their current register to satisfy constraints that are not captured by the machine IR (e.g. ABI or ISA constraints). Reviewers: qcolombet, MatzeB, hfinkel Subscribers: nemanjai, mcrosier, javed.absar, llvm-commits Differential Revision: https://reviews.llvm.org/D39400 llvm-svn: 320503
35 lines
969 B
YAML
35 lines
969 B
YAML
# RUN: llc -verify-machineinstrs -run-pass regallocfast -mtriple s390x-ibm-linux -o - %s | FileCheck %s
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--- |
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@g_167 = external global [5 x i64], align 8
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define void @main() local_unnamed_addr {
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ret void
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}
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...
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# Make sure the usage of different subregisters on the same virtual register
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# does not result in invalid kill flags.
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# PR33677
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---
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name: main
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alignment: 2
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tracksRegLiveness: true
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registers:
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- { id: 0, class: gr128bit }
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- { id: 1, class: gr64bit }
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- { id: 2, class: addr64bit }
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# CHECK: %r0q = L128
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# CHECK-NEXT: %r0l = COPY renamable %r1l
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# Although R0L partially redefines R0Q, it must not mark R0Q as kill
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# because R1D is still live through that instruction.
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# CHECK-NOT: implicit killed %r0q
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# CHECK-NEXT: %r2d = COPY renamable %r1d
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# CHECK-NEXT: LARL
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body: |
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bb.0:
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%0.subreg_hl32 = COPY %0.subreg_l32
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%1 = COPY %0.subreg_l64
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%2 = LARL @g_167
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STC %1.subreg_l32, %2, 8, %noreg
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...
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