Implementation of instructions table.get, table.set, table.grow, table.size, table.fill, table.copy. Missing instructions are table.init and elem.drop as they deal with element sections which are not yet implemented. Added more tests to tables.s Differential Revision: https://reviews.llvm.org/D89797
182 lines
6.6 KiB
C++
182 lines
6.6 KiB
C++
//=- WebAssemblyMCCodeEmitter.cpp - Convert WebAssembly code to machine code -//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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///
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/// \file
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/// This file implements the WebAssemblyMCCodeEmitter class.
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///
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//===----------------------------------------------------------------------===//
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#include "MCTargetDesc/WebAssemblyFixupKinds.h"
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#include "MCTargetDesc/WebAssemblyMCTargetDesc.h"
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#include "llvm/ADT/STLExtras.h"
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#include "llvm/ADT/Statistic.h"
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#include "llvm/MC/MCCodeEmitter.h"
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#include "llvm/MC/MCFixup.h"
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#include "llvm/MC/MCInst.h"
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#include "llvm/MC/MCInstrInfo.h"
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#include "llvm/MC/MCRegisterInfo.h"
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#include "llvm/MC/MCSubtargetInfo.h"
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#include "llvm/MC/MCSymbol.h"
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#include "llvm/Support/Debug.h"
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#include "llvm/Support/EndianStream.h"
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#include "llvm/Support/LEB128.h"
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#include "llvm/Support/raw_ostream.h"
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using namespace llvm;
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#define DEBUG_TYPE "mccodeemitter"
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STATISTIC(MCNumEmitted, "Number of MC instructions emitted.");
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STATISTIC(MCNumFixups, "Number of MC fixups created.");
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namespace {
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class WebAssemblyMCCodeEmitter final : public MCCodeEmitter {
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const MCInstrInfo &MCII;
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// Implementation generated by tablegen.
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uint64_t getBinaryCodeForInstr(const MCInst &MI,
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SmallVectorImpl<MCFixup> &Fixups,
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const MCSubtargetInfo &STI) const;
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void encodeInstruction(const MCInst &MI, raw_ostream &OS,
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SmallVectorImpl<MCFixup> &Fixups,
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const MCSubtargetInfo &STI) const override;
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public:
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WebAssemblyMCCodeEmitter(const MCInstrInfo &MCII) : MCII(MCII) {}
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};
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} // end anonymous namespace
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MCCodeEmitter *llvm::createWebAssemblyMCCodeEmitter(const MCInstrInfo &MCII) {
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return new WebAssemblyMCCodeEmitter(MCII);
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}
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void WebAssemblyMCCodeEmitter::encodeInstruction(
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const MCInst &MI, raw_ostream &OS, SmallVectorImpl<MCFixup> &Fixups,
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const MCSubtargetInfo &STI) const {
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uint64_t Start = OS.tell();
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uint64_t Binary = getBinaryCodeForInstr(MI, Fixups, STI);
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if (Binary <= UINT8_MAX) {
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OS << uint8_t(Binary);
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} else {
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assert(Binary <= UINT16_MAX && "Several-byte opcodes not supported yet");
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OS << uint8_t(Binary >> 8);
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encodeULEB128(uint8_t(Binary), OS);
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}
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// For br_table instructions, encode the size of the table. In the MCInst,
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// there's an index operand (if not a stack instruction), one operand for
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// each table entry, and the default operand.
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if (MI.getOpcode() == WebAssembly::BR_TABLE_I32_S ||
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MI.getOpcode() == WebAssembly::BR_TABLE_I64_S)
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encodeULEB128(MI.getNumOperands() - 1, OS);
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if (MI.getOpcode() == WebAssembly::BR_TABLE_I32 ||
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MI.getOpcode() == WebAssembly::BR_TABLE_I64)
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encodeULEB128(MI.getNumOperands() - 2, OS);
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const MCInstrDesc &Desc = MCII.get(MI.getOpcode());
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for (unsigned I = 0, E = MI.getNumOperands(); I < E; ++I) {
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const MCOperand &MO = MI.getOperand(I);
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if (MO.isReg()) {
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/* nothing to encode */
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} else if (MO.isImm()) {
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if (I < Desc.getNumOperands()) {
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const MCOperandInfo &Info = Desc.OpInfo[I];
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LLVM_DEBUG(dbgs() << "Encoding immediate: type="
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<< int(Info.OperandType) << "\n");
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switch (Info.OperandType) {
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case WebAssembly::OPERAND_I32IMM:
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encodeSLEB128(int32_t(MO.getImm()), OS);
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break;
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case WebAssembly::OPERAND_OFFSET32:
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encodeULEB128(uint32_t(MO.getImm()), OS);
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break;
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case WebAssembly::OPERAND_I64IMM:
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encodeSLEB128(int64_t(MO.getImm()), OS);
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break;
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case WebAssembly::OPERAND_SIGNATURE:
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OS << uint8_t(MO.getImm());
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break;
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case WebAssembly::OPERAND_VEC_I8IMM:
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support::endian::write<uint8_t>(OS, MO.getImm(), support::little);
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break;
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case WebAssembly::OPERAND_VEC_I16IMM:
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support::endian::write<uint16_t>(OS, MO.getImm(), support::little);
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break;
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case WebAssembly::OPERAND_VEC_I32IMM:
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support::endian::write<uint32_t>(OS, MO.getImm(), support::little);
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break;
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case WebAssembly::OPERAND_VEC_I64IMM:
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support::endian::write<uint64_t>(OS, MO.getImm(), support::little);
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break;
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case WebAssembly::OPERAND_GLOBAL:
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llvm_unreachable("wasm globals should only be accessed symbolicly");
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default:
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encodeULEB128(uint64_t(MO.getImm()), OS);
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}
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} else {
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encodeULEB128(uint64_t(MO.getImm()), OS);
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}
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} else if (MO.isFPImm()) {
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const MCOperandInfo &Info = Desc.OpInfo[I];
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if (Info.OperandType == WebAssembly::OPERAND_F32IMM) {
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// TODO: MC converts all floating point immediate operands to double.
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// This is fine for numeric values, but may cause NaNs to change bits.
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auto F = float(MO.getFPImm());
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support::endian::write<float>(OS, F, support::little);
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} else {
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assert(Info.OperandType == WebAssembly::OPERAND_F64IMM);
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double D = MO.getFPImm();
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support::endian::write<double>(OS, D, support::little);
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}
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} else if (MO.isExpr()) {
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const MCOperandInfo &Info = Desc.OpInfo[I];
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llvm::MCFixupKind FixupKind;
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size_t PaddedSize = 5;
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switch (Info.OperandType) {
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case WebAssembly::OPERAND_I32IMM:
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FixupKind = MCFixupKind(WebAssembly::fixup_sleb128_i32);
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break;
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case WebAssembly::OPERAND_I64IMM:
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FixupKind = MCFixupKind(WebAssembly::fixup_sleb128_i64);
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PaddedSize = 10;
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break;
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case WebAssembly::OPERAND_FUNCTION32:
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case WebAssembly::OPERAND_TABLE:
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case WebAssembly::OPERAND_OFFSET32:
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case WebAssembly::OPERAND_SIGNATURE:
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case WebAssembly::OPERAND_TYPEINDEX:
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case WebAssembly::OPERAND_GLOBAL:
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case WebAssembly::OPERAND_EVENT:
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FixupKind = MCFixupKind(WebAssembly::fixup_uleb128_i32);
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break;
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case WebAssembly::OPERAND_OFFSET64:
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FixupKind = MCFixupKind(WebAssembly::fixup_uleb128_i64);
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PaddedSize = 10;
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break;
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default:
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llvm_unreachable("unexpected symbolic operand kind");
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}
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Fixups.push_back(MCFixup::create(OS.tell() - Start, MO.getExpr(),
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FixupKind, MI.getLoc()));
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++MCNumFixups;
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encodeULEB128(0, OS, PaddedSize);
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} else {
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llvm_unreachable("unexpected operand kind");
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}
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}
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++MCNumEmitted; // Keep track of the # of mi's emitted.
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}
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#include "WebAssemblyGenMCCodeEmitter.inc"
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