faca8c9ed4
Saves around 125-210 MB of compilation memory usage per source for roughly one third of our backend sources, ~60 MB on average.
76 lines
2.6 KiB
C++
76 lines
2.6 KiB
C++
//===- llvm/unittests/Target/AMDGPU/CSETest.cpp ---------------------------===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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#include "AMDGPUTargetMachine.h"
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#include "AMDGPUUnitTests.h"
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#include "llvm/CodeGen/GlobalISel/CSEInfo.h"
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#include "llvm/CodeGen/GlobalISel/CSEMIRBuilder.h"
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#include "llvm/CodeGen/MachineModuleInfo.h"
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#include "gtest/gtest.h"
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using namespace llvm;
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TEST(AMDGPU, TestCSEForRegisterClassOrBankAndLLT) {
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auto TM = createAMDGPUTargetMachine("amdgcn-amd-", "gfx1100", "");
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if (!TM)
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GTEST_SKIP();
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GCNSubtarget ST(TM->getTargetTriple(), std::string(TM->getTargetCPU()),
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std::string(TM->getTargetFeatureString()), *TM);
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LLVMContext Ctx;
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Module Mod("Module", Ctx);
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Mod.setDataLayout(TM->createDataLayout());
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auto *Type = FunctionType::get(Type::getVoidTy(Ctx), false);
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auto *F = Function::Create(Type, GlobalValue::ExternalLinkage, "Test", &Mod);
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MachineModuleInfo MMI(TM.get());
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auto MF =
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std::make_unique<MachineFunction>(*F, *TM, ST, MMI.getContext(), 42);
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auto *BB = MF->CreateMachineBasicBlock();
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MF->push_back(BB);
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MachineIRBuilder B(*MF);
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B.setMBB(*BB);
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LLT S32{LLT::scalar(32)};
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Register R0 = B.buildCopy(S32, Register(AMDGPU::SGPR0)).getReg(0);
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Register R1 = B.buildCopy(S32, Register(AMDGPU::SGPR1)).getReg(0);
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GISelCSEInfo CSEInfo;
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CSEInfo.setCSEConfig(std::make_unique<CSEConfigFull>());
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CSEInfo.analyze(*MF);
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B.setCSEInfo(&CSEInfo);
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CSEMIRBuilder CSEB(B.getState());
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CSEB.setInsertPt(B.getMBB(), B.getInsertPt());
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const RegisterBankInfo &RBI = *MF->getSubtarget().getRegBankInfo();
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const TargetRegisterClass *SgprRC = &AMDGPU::SReg_32RegClass;
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const RegisterBank *SgprRB = &RBI.getRegBank(AMDGPU::SGPRRegBankID);
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MachineRegisterInfo::VRegAttrs SgprRCS32 = {SgprRC, S32};
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MachineRegisterInfo::VRegAttrs SgprRBS32 = {SgprRB, S32};
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auto Add = CSEB.buildAdd(S32, R0, R1);
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auto AddRC = CSEB.buildInstr(AMDGPU::G_ADD, {SgprRCS32}, {R0, R1});
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auto AddRB = CSEB.buildInstr(AMDGPU::G_ADD, {{SgprRB, S32}}, {R0, R1});
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EXPECT_NE(Add, AddRC);
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EXPECT_NE(Add, AddRB);
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EXPECT_NE(AddRC, AddRB);
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auto Add_CSE = CSEB.buildAdd(S32, R0, R1);
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auto AddRC_CSE = CSEB.buildInstr(AMDGPU::G_ADD, {{SgprRC, S32}}, {R0, R1});
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auto AddRB_CSE = CSEB.buildInstr(AMDGPU::G_ADD, {SgprRBS32}, {R0, R1});
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EXPECT_EQ(Add, Add_CSE);
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EXPECT_EQ(AddRC, AddRC_CSE);
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EXPECT_EQ(AddRB, AddRB_CSE);
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}
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