d7e23bef6a
lldb-server had limited support for single-stepping through the lr/sc atomic sequence. This patch enhances that support for all possible atomic sequences. The previous version contained an incorrect regex pattern in the test, causing the riscv-specific test to run on other platforms. This reland fixes the regex (see lldb/test/API/riscv/step/TestSoftwareStep.py)
23 lines
670 B
C
23 lines
670 B
C
void __attribute__((naked)) incomplete_cas(int *a, int *b) {
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// Stop at the first instruction (an sc without a corresponding lr), then make
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// a step instruction and ensure that execution stops at the next instruction
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// (and).
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asm volatile("1:\n\t"
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"sc.w a5, a1, (a3)\n\t"
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"and a5, a2, a4\n\t"
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"beq a5, a1, 2f\n\t"
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"xor a5, a2, a0\n\t"
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"and a5, a5, a4\n\t"
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"xor a5, a2, a5\n\t"
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"sc.w a5, a1, (a3)\n\t"
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"bnez a5, 1b\n\t"
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"2:\n\t"
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"ret\n\t");
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}
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int main() {
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int a = 4;
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int b = 2;
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incomplete_cas(&a, &b);
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}
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