8f3e78f971
If we have a v_mov_b32 or v_accvgpr_write_b32 with an inline immediate, replace it with a pseudo which writes to the combined AV_* class. This relaxes the operand constraints, which will allow the allocator to inflate the register class to AV_* to potentially avoid spilling. The allocator does not know how to replace an instruction to enable the change of register class. I originally tried to do this by changing all of the places we introduce v_mov_b32 with immediate, but it's along tail of niche cases that require manual updating. Plus we can restrict this to only run on functions where we know we will be allocating AGPRs.
96 lines
4.2 KiB
YAML
96 lines
4.2 KiB
YAML
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 5
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# RUN: llc -mtriple=amdgcn -mcpu=gfx90a -run-pass=amdgpu-prepare-agpr-alloc -o - %s | FileCheck -check-prefixes=HAS-AGPR,GFX90A %s
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# RUN: llc -mtriple=amdgcn -mcpu=gfx908 -run-pass=amdgpu-prepare-agpr-alloc -o - %s | FileCheck -check-prefixes=HAS-AGPR,GFX908 %s
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# RUN: llc -mtriple=amdgcn -mcpu=gfx906 -passes=amdgpu-prepare-agpr-alloc -o - %s | FileCheck -check-prefix=NO-AGPR %s
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--- |
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define void @func() {
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ret void
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}
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; Attribute is ignored for gfx90a
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define void @no_agprs() "amdgpu-agpr-alloc"="0,0" {
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ret void
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}
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...
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---
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name: func
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tracksRegLiveness: true
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stack:
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- { id: 0, size: 4 }
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body: |
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; HAS-AGPR-LABEL: name: func
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; HAS-AGPR: bb.0:
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; HAS-AGPR-NEXT: successors: %bb.1(0x80000000)
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; HAS-AGPR-NEXT: liveins: $vgpr0
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; HAS-AGPR-NEXT: {{ $}}
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; HAS-AGPR-NEXT: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 $vgpr0, implicit $exec
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; HAS-AGPR-NEXT: [[V_ACCVGPR_WRITE_B32_e64_:%[0-9]+]]:agpr_32 = V_ACCVGPR_WRITE_B32_e64 $vgpr0, implicit $exec
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; HAS-AGPR-NEXT: [[AV_MOV_:%[0-9]+]]:vgpr_32 = AV_MOV_B32_IMM_PSEUDO 1, implicit $exec
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; HAS-AGPR-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 65, implicit $exec
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; HAS-AGPR-NEXT: [[V_MOV_B32_e32_2:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 %stack.0, implicit $exec
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; HAS-AGPR-NEXT: [[AV_MOV_1:%[0-9]+]]:agpr_32 = AV_MOV_B32_IMM_PSEUDO 2, implicit $exec
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; HAS-AGPR-NEXT: [[AV_MOV_2:%[0-9]+]]:agpr_32 = AV_MOV_B32_IMM_PSEUDO 6, implicit $exec
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; HAS-AGPR-NEXT: {{ $}}
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; HAS-AGPR-NEXT: bb.1:
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; HAS-AGPR-NEXT: [[AV_MOV_3:%[0-9]+]]:vgpr_32 = AV_MOV_B32_IMM_PSEUDO 3, implicit $exec
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;
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; NO-AGPR-LABEL: name: func
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; NO-AGPR: bb.0:
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; NO-AGPR-NEXT: successors: %bb.1(0x80000000)
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; NO-AGPR-NEXT: liveins: $vgpr0
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; NO-AGPR-NEXT: {{ $}}
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; NO-AGPR-NEXT: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 $vgpr0, implicit $exec
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; NO-AGPR-NEXT: [[V_ACCVGPR_WRITE_B32_e64_:%[0-9]+]]:agpr_32 = V_ACCVGPR_WRITE_B32_e64 $vgpr0, implicit $exec
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; NO-AGPR-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 1, implicit $exec
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; NO-AGPR-NEXT: [[V_MOV_B32_e32_2:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 65, implicit $exec
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; NO-AGPR-NEXT: [[V_MOV_B32_e32_3:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 %stack.0, implicit $exec
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; NO-AGPR-NEXT: [[V_ACCVGPR_WRITE_B32_e64_1:%[0-9]+]]:agpr_32 = V_ACCVGPR_WRITE_B32_e64 2, implicit $exec
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; NO-AGPR-NEXT: [[V_ACCVGPR_WRITE_B32_e64_2:%[0-9]+]]:agpr_32 = V_ACCVGPR_WRITE_B32_e64 6, implicit $exec
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; NO-AGPR-NEXT: {{ $}}
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; NO-AGPR-NEXT: bb.1:
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; NO-AGPR-NEXT: [[V_MOV_B32_e32_4:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 3, implicit $exec
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bb.0:
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liveins: $vgpr0
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%0:vgpr_32 = V_MOV_B32_e32 $vgpr0, implicit $exec
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%1:agpr_32 = V_ACCVGPR_WRITE_B32_e64 $vgpr0, implicit $exec
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%2:vgpr_32 = V_MOV_B32_e32 1, implicit $exec
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%3:vgpr_32 = V_MOV_B32_e32 65, implicit $exec
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%4:vgpr_32 = V_MOV_B32_e32 %stack.0, implicit $exec
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%5:agpr_32 = V_ACCVGPR_WRITE_B32_e64 2, implicit $exec
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%6:agpr_32 = V_ACCVGPR_WRITE_B32_e64 6, implicit $exec
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bb.1:
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%7:vgpr_32 = V_MOV_B32_e32 3, implicit $exec
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...
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---
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name: no_agprs
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $vgpr0
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; GFX90A-LABEL: name: no_agprs
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; GFX90A: liveins: $vgpr0
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; GFX90A-NEXT: {{ $}}
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; GFX90A-NEXT: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 1, implicit $exec
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; GFX90A-NEXT: [[V_ACCVGPR_WRITE_B32_e64_:%[0-9]+]]:agpr_32 = V_ACCVGPR_WRITE_B32_e64 2, implicit $exec
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;
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; GFX908-LABEL: name: no_agprs
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; GFX908: liveins: $vgpr0
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; GFX908-NEXT: {{ $}}
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; GFX908-NEXT: [[AV_MOV_:%[0-9]+]]:vgpr_32 = AV_MOV_B32_IMM_PSEUDO 1, implicit $exec
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; GFX908-NEXT: [[AV_MOV_1:%[0-9]+]]:agpr_32 = AV_MOV_B32_IMM_PSEUDO 2, implicit $exec
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;
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; NO-AGPR-LABEL: name: no_agprs
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; NO-AGPR: liveins: $vgpr0
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; NO-AGPR-NEXT: {{ $}}
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; NO-AGPR-NEXT: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 1, implicit $exec
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; NO-AGPR-NEXT: [[V_ACCVGPR_WRITE_B32_e64_:%[0-9]+]]:agpr_32 = V_ACCVGPR_WRITE_B32_e64 2, implicit $exec
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%0:vgpr_32 = V_MOV_B32_e32 1, implicit $exec
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%1:agpr_32 = V_ACCVGPR_WRITE_B32_e64 2, implicit $exec
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...
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