45909ec469
The instruction MTVSRBMI set 0x00(or 0xFF) to each byte of VSR based on the bits mask. Using the instruction instead of constant pool can reduce the asm code size and instructions in power10.
24 lines
928 B
LLVM
24 lines
928 B
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
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; Verify whether the generated assembly for the following function includes the mtvsrbmi instruction.
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; vector unsigned char v00FF()
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; {
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; vector unsigned char x = { 0xFF, 0,0,0, 0,0,0,0, 0,0,0,0, 0,0,0,0 };
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; return x;
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; }
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; RUN: llc < %s -ppc-asm-full-reg-names -mtriple=powerpc-ibm-aix -mcpu=pwr10 -verify-machineinstrs \
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; RUN: | FileCheck %s --check-prefix=CHECK
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define dso_local noundef range(i8 -1, 1) <16 x i8> @_Z5v00FFv() {
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; CHECK-NOT: L..CPI0_0:
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; CHECK-NOT: .byte 255 # 0xff
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; CHECK-NOT: .byte 0 # 0x0
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; CHECK-LABEL: _Z5v00FFv:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: mtvsrbmi v2, 1
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; CHECK-NEXT: blr
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entry:
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ret <16 x i8> <i8 -1, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0>
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}
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