33c265ddf7
Generate the GEP with the index type that InstCombine will cast it to but use the knowledge that the index is unsigned.
45 lines
1.7 KiB
LLVM
45 lines
1.7 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
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; RUN: opt -S -passes=simplifycfg -simplifycfg-require-and-preserve-domtree=1 -switch-to-lookup < %s -mtriple=x86_64-apple-darwin12.0.0 | FileCheck %s
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; RUN: opt -S -passes='simplifycfg<switch-to-lookup>' < %s -mtriple=x86_64-apple-darwin12.0.0 | FileCheck %s
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; rdar://17735071
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target datalayout = "e-p:64:64:64-S128-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f16:16:16-f32:32:32-f64:64:64-f128:128:128-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64"
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target triple = "x86_64-apple-darwin12.0.0"
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define i64 @_TFO6reduce1E5toRawfS0_FT_Si(i2) {
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; CHECK-LABEL: @_TFO6reduce1E5toRawfS0_FT_Si(
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; CHECK-NEXT: entry:
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; CHECK-NEXT: [[SWITCH_TABLEIDX:%.*]] = sub i2 [[TMP0:%.*]], -2
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; CHECK-NEXT: [[TMP1:%.*]] = zext i2 [[SWITCH_TABLEIDX]] to i64
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; CHECK-NEXT: [[SWITCH_GEP:%.*]] = getelementptr inbounds [4 x i64], ptr @switch.table._TFO6reduce1E5toRawfS0_FT_Si, i64 0, i64 [[TMP1]]
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; CHECK-NEXT: [[SWITCH_LOAD:%.*]] = load i64, ptr [[SWITCH_GEP]], align 8
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; CHECK-NEXT: ret i64 [[SWITCH_LOAD]]
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;
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entry:
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switch i2 %0, label %1 [
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i2 0, label %2
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i2 1, label %3
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i2 -2, label %4
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i2 -1, label %5
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]
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; <label>:1 ; preds = %entry
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unreachable
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; <label>:2 ; preds = %2
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br label %6
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; <label>:3 ; preds = %4
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br label %6
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; <label>:4 ; preds = %6
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br label %6
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; <label>:5 ; preds = %8
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br label %6
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; <label>:6 ; preds = %3, %5, %7, %9
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%7 = phi i64 [ 3, %5 ], [ 2, %4 ], [ 1, %3 ], [ 0, %2 ]
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ret i64 %7
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}
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