33c265ddf7
Generate the GEP with the index type that InstCombine will cast it to but use the knowledge that the index is unsigned.
243 lines
8.4 KiB
LLVM
243 lines
8.4 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
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; RUN: opt -passes=simplifycfg --switch-to-lookup -S < %s | FileCheck %s
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target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128"
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declare i1 @foo()
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; https://alive2.llvm.org/ce/z/tuxLhJ
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define i1 @switch_lookup_with_small_i1(i64 %x) {
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; CHECK-LABEL: @switch_lookup_with_small_i1(
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; CHECK-NEXT: entry:
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; CHECK-NEXT: [[AND:%.*]] = and i64 [[X:%.*]], 15
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; CHECK-NEXT: [[SWITCH_CAST:%.*]] = trunc i64 [[AND]] to i16
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; CHECK-NEXT: [[SWITCH_SHIFTAMT:%.*]] = mul nuw nsw i16 [[SWITCH_CAST]], 1
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; CHECK-NEXT: [[SWITCH_DOWNSHIFT:%.*]] = lshr i16 1030, [[SWITCH_SHIFTAMT]]
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; CHECK-NEXT: [[SWITCH_MASKED:%.*]] = trunc i16 [[SWITCH_DOWNSHIFT]] to i1
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; CHECK-NEXT: ret i1 [[SWITCH_MASKED]]
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;
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entry:
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%and = and i64 %x, 15
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switch i64 %and, label %default [
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i64 10, label %lor.end
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i64 1, label %lor.end
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i64 2, label %lor.end
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]
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default: ; preds = %entry
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br label %lor.end
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lor.end: ; preds = %entry, %entry, %entry, %default
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%0 = phi i1 [ true, %entry ], [ false, %default ], [ true, %entry ], [ true, %entry ]
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ret i1 %0
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}
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; https://godbolt.org/z/sjbjorKon
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define i8 @switch_lookup_with_small_i8(i64 %x) {
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; CHECK-LABEL: @switch_lookup_with_small_i8(
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; CHECK-NEXT: entry:
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; CHECK-NEXT: [[REM:%.*]] = urem i64 [[X:%.*]], 5
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; CHECK-NEXT: [[SWITCH_CAST:%.*]] = trunc i64 [[REM]] to i40
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; CHECK-NEXT: [[SWITCH_SHIFTAMT:%.*]] = mul nuw nsw i40 [[SWITCH_CAST]], 8
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; CHECK-NEXT: [[SWITCH_DOWNSHIFT:%.*]] = lshr i40 460303, [[SWITCH_SHIFTAMT]]
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; CHECK-NEXT: [[SWITCH_MASKED:%.*]] = trunc i40 [[SWITCH_DOWNSHIFT]] to i8
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; CHECK-NEXT: ret i8 [[SWITCH_MASKED]]
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;
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entry:
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%rem = urem i64 %x, 5
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switch i64 %rem, label %default [
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i64 0, label %sw.bb0
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i64 1, label %sw.bb1
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i64 2, label %sw.bb2
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]
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sw.bb0: ; preds = %entry
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br label %lor.end
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sw.bb1: ; preds = %entry
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br label %lor.end
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sw.bb2: ; preds = %entry
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br label %lor.end
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default: ; preds = %entry
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br label %lor.end
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lor.end:
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%0 = phi i8 [ 15, %sw.bb0 ], [ 6, %sw.bb1 ], [ 7, %sw.bb2 ], [ 0, %default ]
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ret i8 %0
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}
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; Negative test: Table size would not fit the register.
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define i8 @switch_lookup_with_small_i8_negative(i64 %x) {
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; CHECK-LABEL: @switch_lookup_with_small_i8_negative(
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; CHECK-NEXT: entry:
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; CHECK-NEXT: [[REM:%.*]] = urem i64 [[X:%.*]], 9
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; CHECK-NEXT: [[TMP0:%.*]] = icmp ult i64 [[REM]], 3
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; CHECK-NEXT: [[SWITCH_CAST:%.*]] = trunc i64 [[REM]] to i24
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; CHECK-NEXT: [[SWITCH_SHIFTAMT:%.*]] = mul nuw nsw i24 [[SWITCH_CAST]], 8
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; CHECK-NEXT: [[SWITCH_DOWNSHIFT:%.*]] = lshr i24 460303, [[SWITCH_SHIFTAMT]]
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; CHECK-NEXT: [[SWITCH_MASKED:%.*]] = trunc i24 [[SWITCH_DOWNSHIFT]] to i8
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; CHECK-NEXT: [[TMP1:%.*]] = select i1 [[TMP0]], i8 [[SWITCH_MASKED]], i8 0
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; CHECK-NEXT: ret i8 [[TMP1]]
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;
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entry:
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%rem = urem i64 %x, 9 ; 9 * 8 = 72 > 64, not fit the register
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switch i64 %rem, label %default [
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i64 0, label %sw.bb0
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i64 1, label %sw.bb1
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i64 2, label %sw.bb2
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]
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sw.bb0: ; preds = %entry
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br label %lor.end
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sw.bb1: ; preds = %entry
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br label %lor.end
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sw.bb2: ; preds = %entry
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br label %lor.end
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default: ; preds = %entry
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br label %lor.end
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lor.end:
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%0 = phi i8 [ 15, %sw.bb0 ], [ 6, %sw.bb1 ], [ 7, %sw.bb2 ], [ 0, %default ]
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ret i8 %0
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}
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; Negative test: The default branch is unreachable, also it has no result.
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define i1 @switch_lookup_with_small_i1_default_unreachable(i32 %x) {
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; CHECK-LABEL: @switch_lookup_with_small_i1_default_unreachable(
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; CHECK-NEXT: entry:
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; CHECK-NEXT: [[AND:%.*]] = and i32 [[X:%.*]], 15
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; CHECK-NEXT: ret i1 false
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;
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entry:
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%and = and i32 %x, 15
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switch i32 %and, label %default [
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i32 4, label %phi.end
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i32 2, label %phi.end
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i32 10, label %phi.end
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i32 9, label %phi.end
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i32 1, label %sw.bb1.i
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i32 3, label %sw.bb1.i
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i32 5, label %sw.bb1.i
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i32 0, label %sw.bb1.i
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i32 6, label %sw.bb1.i
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i32 7, label %sw.bb1.i
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i32 8, label %sw.bb1.i
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]
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sw.bb1.i: ; preds = %entry, %entry, %entry, %entry, %entry, %entry, %entry
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br label %phi.end
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default: ; preds = %entry
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unreachable
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phi.end: ; preds = %sw.bb1.i, %entry, %entry, %entry, %entry
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%retval = phi i1 [ false, %sw.bb1.i ], [ false, %entry ], [ false, %entry ], [ false, %entry ], [ false, %entry ]
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ret i1 %retval
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}
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; Negative test: The result in default reachable, but its value is not const.
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define i1 @switch_lookup_with_small_i1_default_nonconst(i64 %x) {
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; CHECK-LABEL: @switch_lookup_with_small_i1_default_nonconst(
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; CHECK-NEXT: entry:
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; CHECK-NEXT: [[AND:%.*]] = and i64 [[X:%.*]], 15
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; CHECK-NEXT: switch i64 [[AND]], label [[DEFAULT:%.*]] [
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; CHECK-NEXT: i64 10, label [[LOR_END:%.*]]
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; CHECK-NEXT: i64 1, label [[LOR_END]]
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; CHECK-NEXT: i64 2, label [[LOR_END]]
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; CHECK-NEXT: ]
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; CHECK: default:
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; CHECK-NEXT: [[CALL:%.*]] = tail call i1 @foo()
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; CHECK-NEXT: br label [[LOR_END]]
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; CHECK: lor.end:
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; CHECK-NEXT: [[TMP0:%.*]] = phi i1 [ true, [[ENTRY:%.*]] ], [ [[CALL]], [[DEFAULT]] ], [ true, [[ENTRY]] ], [ true, [[ENTRY]] ]
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; CHECK-NEXT: ret i1 [[TMP0]]
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;
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entry:
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%and = and i64 %x, 15
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switch i64 %and, label %default [
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i64 10, label %lor.end
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i64 1, label %lor.end
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i64 2, label %lor.end
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]
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default: ; preds = %entry
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%call = tail call i1 @foo()
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br label %lor.end
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lor.end: ; preds = %entry, %entry, %entry, %default
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%0 = phi i1 [ true, %entry ], [ %call, %default ], [ true, %entry ], [ true, %entry ]
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ret i1 %0
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}
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; Negative test: The upper bound index of switch is swapped.
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define void @switch_lookup_with_nonconst_range(i32 %x, i1 %cond) {
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; CHECK-LABEL: @switch_lookup_with_nonconst_range(
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; CHECK-NEXT: entry:
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; CHECK-NEXT: br label [[FOR_PREHEADER:%.*]]
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; CHECK: for.preheader:
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; CHECK-NEXT: [[ADD:%.*]] = add nuw i32 [[X:%.*]], 1
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; CHECK-NEXT: br i1 [[COND:%.*]], label [[FOR_PREHEADER]], label [[FOR_END:%.*]]
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; CHECK: for.end:
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; CHECK-NEXT: [[TMP0:%.*]] = icmp ult i32 [[ADD]], 6
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; CHECK-NEXT: br i1 [[TMP0]], label [[SWITCH_LOOKUP:%.*]], label [[LOR_END:%.*]]
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; CHECK: switch.lookup:
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; CHECK-NEXT: [[TMP1:%.*]] = zext i32 [[ADD]] to i64
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; CHECK-NEXT: [[SWITCH_GEP:%.*]] = getelementptr inbounds [6 x i32], ptr @switch.table.switch_lookup_with_nonconst_range, i64 0, i64 [[TMP1]]
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; CHECK-NEXT: [[SWITCH_LOAD:%.*]] = load i32, ptr [[SWITCH_GEP]], align 4
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; CHECK-NEXT: br label [[LOR_END]]
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; CHECK: lor.end:
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; CHECK-NEXT: [[RETVAL_0_I_I:%.*]] = phi i32 [ [[SWITCH_LOAD]], [[SWITCH_LOOKUP]] ], [ 1, [[FOR_END]] ]
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; CHECK-NEXT: ret void
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;
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entry:
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br label %for.preheader
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for.preheader: ; preds = %for.preheader, %entry
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%add = add nuw i32 %x, 1 ; the UpperBound is unconfirmed
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br i1 %cond, label %for.preheader, label %for.end
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for.end: ; preds = %for.preheader
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switch i32 %add, label %default [
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i32 0, label %lor.end
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i32 1, label %lor.end
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i32 5, label %lor.end
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]
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default: ; preds = %for.end
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br label %lor.end
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lor.end: ; preds = %default, %for.end, %for.end, %for.end
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%retval.0.i.i = phi i32 [ 1, %default ], [ 0, %for.end ], [ 0, %for.end ], [ 0, %for.end ]
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ret void
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}
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define i1 @pr88607() {
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; CHECK-LABEL: @pr88607(
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; CHECK-NEXT: entry:
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; CHECK-NEXT: [[COND:%.*]] = select i1 false, i32 4, i32 1
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; CHECK-NEXT: [[SPEC_SELECT:%.*]] = select i1 false, i32 2, i32 [[COND]]
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; CHECK-NEXT: ret i1 false
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;
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entry:
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%cond = select i1 false, i32 4, i32 1
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%spec.select = select i1 false, i32 2, i32 %cond
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switch i32 %spec.select, label %lor.rhs [
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i32 0, label %exit
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i32 5, label %exit ; unreachable large case index
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i32 1, label %exit
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]
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lor.rhs: ; preds = %entry
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br label %exit
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exit: ; preds = %lor.rhs, %entry, %entry, %entry, %entry
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%res.ph = phi i1 [ false, %entry ], [ false, %lor.rhs ], [ false, %entry ], [ false, %entry ]
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ret i1 %res.ph
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}
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