Michael Liao c3492a1aa1 [amdgpu] Lower SGPR-to-VGPR copy in the final phase of ISel.
- Need to lower COPY from SGPR to VGPR to a real instruction as the
  standard COPY is used where the source and destination are from the
  same register bank so that we potentially coalesc them together and
  save one COPY. Considering that, backend optimizations, such as CSE,
  won't handle them. However, the copy from SGPR to VGPR always needs
  materializing to a native instruction, it should be lowered into a
  real one before other backend optimizations.

Differential Revision: https://reviews.llvm.org/D87556
2020-09-17 11:04:17 -04:00
..
2019-06-20 15:08:34 +00:00
2019-05-08 22:09:57 +00:00
2020-08-09 20:50:30 +02:00
2019-06-20 15:08:34 +00:00
2020-08-09 20:50:30 +02:00
2020-08-09 20:50:30 +02:00
2020-06-25 10:38:23 +02:00
2020-08-09 20:50:30 +02:00
2020-08-09 20:50:30 +02:00
2019-09-25 18:50:34 +00:00
2019-03-19 15:50:24 +00:00
2019-07-01 17:17:45 +00:00
2020-09-14 13:40:17 +01:00
2020-08-05 12:36:26 -07:00
2020-08-05 12:36:26 -07:00
2019-03-12 21:02:54 +00:00
2020-08-05 12:36:26 -07:00
2020-08-05 12:36:26 -07:00
2020-06-15 16:18:05 -07:00
2020-08-09 20:50:30 +02:00
2020-06-15 16:18:05 -07:00
2019-07-11 21:19:33 +00:00
2019-03-19 15:50:24 +00:00
2019-04-26 16:37:51 +00:00
2020-09-14 13:40:17 +01:00
2020-09-14 13:40:17 +01:00
2019-03-19 15:50:24 +00:00
2019-07-15 17:50:31 +00:00
2020-06-15 16:18:05 -07:00
2020-09-15 19:13:39 -07:00
2019-06-20 15:08:34 +00:00
2019-05-08 22:09:57 +00:00
2019-05-03 15:37:07 +00:00
2020-08-09 20:50:30 +02:00
2018-06-27 15:33:33 +00:00
2020-08-09 20:50:30 +02:00
2020-06-25 10:38:23 +02:00
2020-08-09 20:50:30 +02:00
2020-08-09 20:50:30 +02:00
2019-06-20 15:08:34 +00:00
2020-08-09 20:50:30 +02:00
2020-06-04 17:49:00 -04:00
2020-06-04 17:49:00 -04:00
2020-06-04 17:49:00 -04:00
2020-06-04 17:49:00 -04:00
2020-06-04 17:49:00 -04:00
2020-06-04 17:49:00 -04:00
2020-06-04 17:49:00 -04:00
2020-06-04 17:49:00 -04:00
2019-06-20 15:08:34 +00:00
2019-05-03 15:37:07 +00:00
2020-04-03 10:07:21 +01:00
2020-08-09 20:50:30 +02:00
2020-08-09 20:50:30 +02:00
2020-06-15 16:18:05 -07:00
2020-08-09 20:50:30 +02:00
2020-08-09 20:50:30 +02:00
2020-06-15 16:18:05 -07:00
2020-08-09 20:50:30 +02:00
2020-01-12 22:44:51 -05:00

+==============================================================================+
| How to organize the lit tests                                                |
+==============================================================================+

- If you write a test for matching a single DAG opcode or intrinsic, it should
  go in a file called {opcode_name,intrinsic_name}.ll (e.g. fadd.ll)

- If you write a test that matches several DAG opcodes and checks for a single
  ISA instruction, then that test should go in a file called {ISA_name}.ll (e.g.
  bfi_int.ll

- For all other tests, use your best judgement for organizing tests and naming
  the files.

+==============================================================================+
| Naming conventions                                                           |
+==============================================================================+

- Use dash '-' and not underscore '_' to separate words in file names, unless
  the file is named after a DAG opcode or ISA instruction that has an
  underscore '_' in its name.