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llvm-project/llvm/lib/Target/RISCV
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Michael Maitland 58f1640635
[RISCV][llvm-mca] Use correct LMUL and SEW for strided loads and stores (#76869) 
The pseudos for strided loads and stores use the SEW coming from the
name. For example, vlse8 has SEW=8 and vlse16 has SEW=16.

When llvm-mca tries to lookup (VLSE8_V, SEW=S, LMUL=L) in the inverse
pseudo table, a result will only be found when S=8, where S was set from
the previous vsetvli instruction. Instead, for a match to be found, we
must lookup (VLSE8_V, SEW=8, LMUL=L') where L' is the EMUL which was
calculated by scaling the LMUL and SEW from the previous vsetvli and the
SEW=8.
2024-01-04 15:40:30 -05:00
..
AsmParser
[RISCV] Remove XSfcie extension.
2023-12-28 13:54:15 -08:00
Disassembler
[RISCV] Add MC layer support for Zicfiss. (#66043)
2023-12-30 15:40:20 +08:00
GISel
[GlobalISel][AArch64] Tail call libcalls. (#74929)
2024-01-03 07:59:36 +00:00
MCA
[RISCV][llvm-mca] Use correct LMUL and SEW for strided loads and stores (#76869)
2024-01-04 15:40:30 -05:00
MCTargetDesc
[RISCV] Remove XSfcie extension.
2023-12-28 13:54:15 -08:00
TargetInfo
…
CMakeLists.txt
[RISCV] Add missing component Scalar (#71905)
2023-11-10 16:43:42 +08:00
RISCV.h
[Target] Remove unused forward declarations (NFC)
2023-12-10 10:38:55 -08:00
RISCV.td
…
RISCVAsmPrinter.cpp
[RISCV] Add Stackmap/Statepoint/Patchpoint support without targets
2023-10-11 09:18:55 +05:30
RISCVCallingConv.td
[RISCV] Remove gp and tp from callee saved register lists. (#76483)
2023-12-27 21:36:03 -08:00
RISCVCodeGenPrepare.cpp
[RISCV][CodeGenPrepare] Remove duplicated transform for zext. NFC. (#72053)
2023-11-13 22:45:33 +08:00
RISCVCombine.td
[RISCV][GISel] Add a post legalizer combiner and enable a couple comb… (#67053)
2023-09-22 10:13:56 -07:00
RISCVDeadRegisterDefinitions.cpp
[RISCV] Cleanup pass initialization.
2023-12-07 18:21:38 -08:00
RISCVExpandAtomicPseudoInsts.cpp
[RISCV] Prevent tryToFoldBNEOnCmpXchgResult from deleting AND if it has others users.
2023-08-28 10:11:12 -07:00
RISCVExpandPseudoInsts.cpp
[RISCV] Cleanup pass initialization.
2023-12-07 18:21:38 -08:00
RISCVFeatures.td
[RISCV] Add MC layer support for Zicfiss. (#66043)
2023-12-30 15:40:20 +08:00
RISCVFoldMasks.cpp
[RISCV] Cleanup pass initialization.
2023-12-07 18:21:38 -08:00
RISCVFrameLowering.cpp
[RISCV] Remove null terminator from CSRegs in determineCalleeSaves. NFC (#74131)
2023-12-01 14:05:55 -08:00
RISCVFrameLowering.h
[llvm] Fix duplicate word typos. NFC
2023-09-01 18:25:16 -07:00
RISCVGatherScatterLowering.cpp
[IR] Fix GEP offset computations for vector GEPs (#75448)
2024-01-04 10:08:21 +01:00
RISCVGISel.td
[RISCV][GISel] Support G_ROTL/G_ROTR with Zbb. (#72825)
2023-12-04 13:00:34 -08:00
RISCVInsertReadWriteCSR.cpp
[RISCV] Cleanup pass initialization.
2023-12-07 18:21:38 -08:00
RISCVInsertVSETVLI.cpp
[RISCV][InsertVSETVLI] Factor out isNonZeroLoadImmediate helper [nfc]
2023-12-15 11:20:01 -08:00
RISCVInsertWriteVXRM.cpp
[RISCV] Don't emit vxrm writes for vnclip(u).wi with shift of 0. (#76578)
2024-01-02 09:50:06 -08:00
RISCVInstrFormats.td
[RISCV] Move Zimop to RISCVInstrInfoZimop.td (#76392)
2023-12-27 11:19:38 +08:00
RISCVInstrFormatsC.td
[RISCV] Remove unused Opcode field from RVInst16. NFC
2023-07-20 08:18:06 -07:00
RISCVInstrFormatsV.td
[RISCV] Remove Opcode field from RVInst. Assign Inst{6-0} directly. NFC
2023-07-20 08:18:06 -07:00
RISCVInstrGISel.td
[RISCV][GISel] Add support for G_IS_FPCLASS in F and D extensions (#72000)
2023-11-22 16:43:20 -08:00
RISCVInstrInfo.cpp
[RISCV] Change heuristic used for load clustering (#75341)
2024-01-02 16:28:24 +00:00
RISCVInstrInfo.h
[MachineScheduler][NFCI] Add Offset and OffsetIsScalable args to shouldClusterMemOps (#73778)
2023-12-06 15:30:48 +00:00
RISCVInstrInfo.td
[RISCV] Add MC layer support for Zicfiss. (#66043)
2023-12-30 15:40:20 +08:00
RISCVInstrInfoA.td
[RISCV] Add IsSignExtendingOpW to LR_W and SC_W as well. NFC
2023-11-15 09:56:36 -08:00
RISCVInstrInfoC.td
[RISCV] Add CompressPat for c.beqz/bnez with X0 in the first operand. (#69042)
2023-10-14 08:12:46 -07:00
RISCVInstrInfoD.td
[RISCV][NFC] Rename RISCVISD::FPCLASS to RISCVISD::FCLASS
2023-11-22 16:24:05 -08:00
RISCVInstrInfoF.td
[RISCV][NFC] Rename RISCVISD::FPCLASS to RISCVISD::FCLASS
2023-11-22 16:24:05 -08:00
RISCVInstrInfoM.td
[RISCV] Add experimental support for making i32 a legal type on RV64 in SelectionDAG. (#70357)
2023-11-01 09:36:41 -07:00
RISCVInstrInfoV.td
[RISCV][NFC] Add base classes of Operand and uimm/simm (#68472)
2023-10-08 14:13:08 +08:00
RISCVInstrInfoVPseudos.td
[RISCV] Add overlapping constraints flag to RVV pseudo (#76489)
2024-01-02 21:39:08 +08:00
RISCVInstrInfoVSDPatterns.td
[RISCV] Support select/merge like ops for fp16 vectors when only have Zvfhmin
2023-09-27 14:53:14 +08:00
RISCVInstrInfoVVLPatterns.td
[RISCV] Remove RISCVISD::VSELECT_VL. (#76866)
2024-01-03 21:31:07 -08:00
RISCVInstrInfoXCV.td
[RISCV] Implement intrinsics for XCVbitmanip extension in CV32E40P (#74993)
2023-12-17 19:29:40 +08:00
RISCVInstrInfoXSf.td
[RISCV] Remove XSfcie extension.
2023-12-28 13:54:15 -08:00
RISCVInstrInfoXTHead.td
[RISCV] Add experimental support for making i32 a legal type on RV64 in SelectionDAG. (#70357)
2023-11-01 09:36:41 -07:00
RISCVInstrInfoXVentana.td
[RISCV] Rename Ventana DecoderNamespace to XVentana for matching other extension. NFC.
2023-08-19 12:44:59 +08:00
RISCVInstrInfoZb.td
[RISCV] Add more Zbs patterns for -riscv-experimental-rv64-legal-i32.
2023-11-21 23:24:00 -08:00
RISCVInstrInfoZc.td
[RISCV] Update DecoderMethod and MCOperandPredicate of spimm. (#76061)
2023-12-27 09:11:34 +08:00
RISCVInstrInfoZcmop.td
[RISCV] Add MC layer support for Zicfiss. (#66043)
2023-12-30 15:40:20 +08:00
RISCVInstrInfoZfa.td
[RISCV] Apply IsSignExtendingOpW = 1 on fcvtmod.w.d (#69633)
2023-10-19 14:55:33 -07:00
RISCVInstrInfoZfbfmin.td
[RISCV] Add experimental support for making i32 a legal type on RV64 in SelectionDAG. (#70357)
2023-11-01 09:36:41 -07:00
RISCVInstrInfoZfh.td
[RISCV][NFC] Rename RISCVISD::FPCLASS to RISCVISD::FCLASS
2023-11-22 16:24:05 -08:00
RISCVInstrInfoZicbo.td
[RISCV] Match prefetch address with offset (#66072)
2023-10-20 14:22:48 +08:00
RISCVInstrInfoZicfiss.td
[RISCV] Add MC layer support for Zicfiss. (#66043)
2023-12-30 15:40:20 +08:00
RISCVInstrInfoZicond.td
[RISCV] Handle seteq/setne conditions for CZERO_NEZ/CZERO_EQZ during isel.
2023-07-26 10:06:08 -07:00
RISCVInstrInfoZimop.td
[RISCV] Move Zimop to RISCVInstrInfoZimop.td (#76392)
2023-12-27 11:19:38 +08:00
RISCVInstrInfoZk.td
[RISCV][NFC] Add base classes of Operand and uimm/simm (#68472)
2023-10-08 14:13:08 +08:00
RISCVInstrInfoZvfbf.td
[RISCV] Model all 3 arithmetic sources of vector FMA at MC layer.
2023-08-04 09:08:16 -07:00
RISCVInstrInfoZvk.td
[RISCV] Remove experimental from Vector Crypto extensions (#74213)
2023-12-18 22:04:22 -08:00
RISCVISelDAGToDAG.cpp
[RISCV] Remove incomplete PRE_DEC/POST_DEC code for XTHeadMemIdx. (#76922)
2024-01-04 09:48:40 -08:00
RISCVISelDAGToDAG.h
[RISCV] Disable performCombineVMergeAndVOps for PseduoVIOTA_M. (#71483)
2023-11-07 16:21:35 +08:00
RISCVISelLowering.cpp
[RISCV] Remove incomplete PRE_DEC/POST_DEC code for XTHeadMemIdx. (#76922)
2024-01-04 09:48:40 -08:00
RISCVISelLowering.h
[RISCV] Remove incomplete PRE_DEC/POST_DEC code for XTHeadMemIdx. (#76922)
2024-01-04 09:48:40 -08:00
RISCVMachineFunctionInfo.cpp
…
RISCVMachineFunctionInfo.h
[RISCV] Fix wrong offset use caused by missing the size of Zcmp push. (#66613)
2023-09-25 12:05:05 +08:00
RISCVMacroFusion.cpp
[RISCV] Split TuneShiftedZExtFusion (#76032)
2023-12-22 14:37:26 +08:00
RISCVMacroFusion.h
…
RISCVMakeCompressible.cpp
[RISCV] Cleanup pass initialization.
2023-12-07 18:21:38 -08:00
RISCVMergeBaseOffset.cpp
[Target] Remove unnecessary includes (NFC)
2023-12-07 21:03:56 -08:00
RISCVMoveMerger.cpp
[RISCV] Cleanup pass initialization.
2023-12-07 18:21:38 -08:00
RISCVOptWInstrs.cpp
[RISCV] Cleanup pass initialization.
2023-12-07 18:21:38 -08:00
RISCVPostRAExpandPseudoInsts.cpp
[RISCV][NFC] Pass MCSubtargetInfo instead of FeatureBitset in RISCVMatInt (#71770)
2023-11-09 15:15:23 +08:00
RISCVProcessors.td
[RISCV] Remove XSfcie extension.
2023-12-28 13:54:15 -08:00
RISCVPushPopOptimizer.cpp
[RISCV] Cleanup pass initialization.
2023-12-07 18:21:38 -08:00
RISCVRedundantCopyElimination.cpp
…
RISCVRegisterInfo.cpp
[RISCV] Add MC layer support for Zicfiss. (#66043)
2023-12-30 15:40:20 +08:00
RISCVRegisterInfo.h
…
RISCVRegisterInfo.td
[RISCV] Add MC layer support for Zicfiss. (#66043)
2023-12-30 15:40:20 +08:00
RISCVRVVInitUndef.cpp
[RISCV] Cleanup pass initialization.
2023-12-07 18:21:38 -08:00
RISCVSchedRocket.td
[RISCV] Separate addend from FMA operands to support cascade FMA. NFC. (#70241)
2023-10-26 13:00:36 +08:00
RISCVSchedSiFive7.td
[RISCV][MISched] Set EnableIntervals to true for SiFive7 (#75681)
2023-12-19 11:03:03 -05:00
RISCVSchedSyntacoreSCR1.td
[RISCV] Separate addend from FMA operands to support cascade FMA. NFC. (#70241)
2023-10-26 13:00:36 +08:00
RISCVSchedule.td
[RISCV] Separate addend from FMA operands to support cascade FMA. NFC. (#70241)
2023-10-26 13:00:36 +08:00
RISCVScheduleV.td
[RISCV] Remove SiFive7PipeV and replace it with SiFive7VCQ (#73969)
2023-12-04 17:21:02 -05:00
RISCVScheduleZb.td
[RISCV] Split BEXT and BEXTI Write classes. NFC.
2023-07-17 15:52:40 -07:00
RISCVSubtarget.cpp
[RISCV] Add MinimumJumpTableEntries to TuneInfo (#72963)
2023-11-23 14:05:23 +08:00
RISCVSubtarget.h
[RISCV] Split TuneShiftedZExtFusion (#76032)
2023-12-22 14:37:26 +08:00
RISCVSystemOperands.td
[RISCV] Remove XSfcie extension.
2023-12-28 13:54:15 -08:00
RISCVTargetMachine.cpp
[RISCV][NFC] Use raw_svector_ostream to construct key of SubtargetMap (#72964)
2023-12-08 18:34:31 +08:00
RISCVTargetMachine.h
[NFC][CodeGen] Change CodeGenOpt::Level/CodeGenFileType into enum classes (#66295)
2023-09-14 14:10:14 -07:00
RISCVTargetObjectFile.cpp
…
RISCVTargetObjectFile.h
…
RISCVTargetTransformInfo.cpp
[RISCV][CostModel] Add getRISCVInstructionCost() to TTI for CostKind (#76793)
2024-01-04 21:04:36 +08:00
RISCVTargetTransformInfo.h
[RISCV][CostModel] Add getRISCVInstructionCost() to TTI for CostKind (#76793)
2024-01-04 21:04:36 +08:00