Shih-Po Hung 475890cd2e

[RISCV][CostModel] Add getRISCVInstructionCost() to TTI for CostKind (#76793) ...

Instruction cost for CodeSize and Latency/RecipThroughput can be very
different. Considering the diversity of CostKind and vendor-specific
cost, and how they are spread across various TTI functions, it's
becoming quite a challenge to handle. This patch adds an interface
getRISCVInstructionCost to address it.

2024-01-04 21:04:36 +08:00

..

AArch64

[DAG] narrowExtractedVectorBinOp - ensure we limit late node creation to LegalOperations only (#72130)

2023-11-20 10:56:41 +00:00

AMDGPU

[AMDGPU] Generic lowering for rint and nearbyint (#69596)

2023-11-14 18:49:21 +01:00

ARM

[CostModel] Mark ssa_copy as free (#75294)

2023-12-13 11:24:47 +00:00

PowerPC

[opt] Infer DataLayout from triple if not specified

2023-10-26 12:07:37 -07:00

RISCV

[RISCV][CostModel] Add getRISCVInstructionCost() to TTI for CostKind (#76793)

2024-01-04 21:04:36 +08:00

SystemZ

[opt] Infer DataLayout from triple if not specified

2023-10-26 12:07:37 -07:00

X86

[CostModel][X86] Update SSSE3/AVX1 BSWAP costs

2024-01-02 12:06:48 +00:00

free-intrinsics-datalayout.ll

[Assignment Tracking] getIntrinsicInstrCost: set dbg.assign cost to zero

2023-03-14 09:26:29 +00:00

free-intrinsics-no_info.ll

[Assignment Tracking] getIntrinsicInstrCost: set dbg.assign cost to zero

2023-03-14 09:26:29 +00:00

no_info.ll

[CostModel] Convert some tests to opaque pointers (NFC)

2022-12-15 09:50:34 +01:00