shylie/llvm-project

History

Maksim Levental a0c19bd455

[mlir][RegionBranchOpInterface] explicitly check for existance of block terminator (#76831 )

2024-01-04 14:43:52 -06:00

..

benchmark/python

[mlir][benchmark] Fix broken benchmark script (#68841 )

2023-12-06 12:17:53 +05:30

Revert "[mlir] Consider mlir-linalg-ods-gen as a tablegen tool in build (#75093 )"

2024-01-04 02:01:16 +05:00

[mlir][TD] Fix the order of return handles (#76929 )

2024-01-04 12:54:16 +00:00

[mlir] Add config for PDL (#69927 )

2024-01-03 20:37:20 -08:00

[mlir][openacc][NFC] Rename custom parser from WaitOperands to DeviceTypeOperandsWithSegment

2024-01-04 10:28:37 -08:00

[mlir][RegionBranchOpInterface] explicitly check for existance of block terminator (#76831 )

2024-01-04 14:43:52 -06:00

Slightly improved ir.pyi type annotations (#76728 )

2024-01-04 09:49:57 +01:00

[mlir][RegionBranchOpInterface] explicitly check for existance of block terminator (#76831 )

2024-01-04 14:43:52 -06:00

[mlir] Add config for PDL (#69927 )

2024-01-03 20:37:20 -08:00

[mlir] add a way to query non-property attributes (#76959 )

2024-01-04 16:40:13 +01:00

[mlir][arith] Rename operations: maxf → maximumf, minf → minimumf (#65800 )

2023-09-11 22:02:19 -07:00

.clang-format

[mlir] Add missing newline at end of .clang-format file

2022-06-14 23:59:00 -07:00

.clang-tidy

[mlir] Disable misc-const-correctness clang-tidy check.

2022-08-03 10:18:43 +02:00

CMakeLists.txt

[mlir] Add config for PDL (#69927 )

2024-01-03 20:37:20 -08:00

LICENSE.TXT

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README.md

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README.md

Multi-Level Intermediate Representation

See https://mlir.llvm.org/ for more information.