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llvm-project/llvm/lib/Target/AArch64
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Evandro Menezes 14fa2e4fa5 [AArch64] Improve single vector lane stores 
When storing the 0th lane of a vector, use a simpler and usually more efficient scalar store instead.

Differential revision: https://reviews.llvm.org/D46655

llvm-svn: 332251
2018-05-14 15:26:35 +00:00
..
AsmParser
[AArch64][SVE] Extend parsing of Prefetch operation for SVE.
2018-05-14 11:54:41 +00:00
Disassembler
[AArch64][SVE] Asm: Support for contiguous LD1 (scalar+scalar) load instructions.
2018-04-20 12:52:01 +00:00
InstPrinter
[AArch64][SVE] Extend parsing of Prefetch operation for SVE.
2018-05-14 11:54:41 +00:00
MCTargetDesc
[COFF, ARM64] Hook up a few remaining relocations
2018-05-02 18:24:37 +00:00
TargetInfo
Add backend name to Target to enable runtime info to be fed back into TableGen
2017-11-15 23:55:44 +00:00
Utils
[AArch64][SVE] Extend parsing of Prefetch operation for SVE.
2018-05-14 11:54:41 +00:00
AArch64.h
Revert r331816 and r331820 - [globalisel] Add a combiner helpers for extending loads and use them in a pre-legalize combiner for AArch64
2018-05-09 05:00:17 +00:00
AArch64.td
[PATCH] [AArch64] Add new target feature to fuse conditional select
2018-02-23 19:27:43 +00:00
AArch64A53Fix835769.cpp
Rename DEBUG macro to LLVM_DEBUG.
2018-05-14 12:53:11 +00:00
AArch64A57FPLoadBalancing.cpp
Rename DEBUG macro to LLVM_DEBUG.
2018-05-14 12:53:11 +00:00
AArch64AdvSIMDScalarPass.cpp
Rename DEBUG macro to LLVM_DEBUG.
2018-05-14 12:53:11 +00:00
AArch64AsmPrinter.cpp
Remove \brief commands from doxygen comments.
2018-05-01 15:54:18 +00:00
AArch64CallingConvention.h
Target/TargetInstrInfo.h -> CodeGen/TargetInstrInfo.h to match layering
2017-11-08 01:01:31 +00:00
AArch64CallingConvention.td
AArch64: Implement support for the shadowcallstack attribute.
2018-04-04 21:55:44 +00:00
AArch64CallLowering.cpp
[IR][CodeGen] Remove dependency on EVT from IR/Function.cpp. Move EVT to CodeGen layer.
2018-03-29 17:21:10 +00:00
AArch64CallLowering.h
GlobalISel (AArch64): fix ABI at border between GPRs and SP.
2017-08-21 21:56:11 +00:00
AArch64CleanupLocalDynamicTLSPass.cpp
MachineFunction: Return reference from getFunction(); NFC
2017-12-15 22:22:58 +00:00
AArch64CollectLOH.cpp
Rename DEBUG macro to LLVM_DEBUG.
2018-05-14 12:53:11 +00:00
AArch64CondBrTuning.cpp
Rename DEBUG macro to LLVM_DEBUG.
2018-05-14 12:53:11 +00:00
AArch64ConditionalCompares.cpp
Rename DEBUG macro to LLVM_DEBUG.
2018-05-14 12:53:11 +00:00
AArch64ConditionOptimizer.cpp
Rename DEBUG macro to LLVM_DEBUG.
2018-05-14 12:53:11 +00:00
AArch64DeadRegisterDefinitionsPass.cpp
Rename DEBUG macro to LLVM_DEBUG.
2018-05-14 12:53:11 +00:00
AArch64ExpandPseudoInsts.cpp
Remove \brief commands from doxygen comments.
2018-05-01 15:54:18 +00:00
AArch64FalkorHWPFFix.cpp
Rename DEBUG macro to LLVM_DEBUG.
2018-05-14 12:53:11 +00:00
AArch64FastISel.cpp
Remove \brief commands from doxygen comments.
2018-05-01 15:54:18 +00:00
AArch64FrameLowering.cpp
Rename DEBUG macro to LLVM_DEBUG.
2018-05-14 12:53:11 +00:00
AArch64FrameLowering.h
Remove \brief commands from doxygen comments.
2018-05-01 15:54:18 +00:00
AArch64GenRegisterBankInfo.def
[AArch64][RegisterBankInfo] Teach instruction mapping about gpr32 -> fpr16 cross copies
2017-11-18 04:28:56 +00:00
AArch64InstrAtomics.td
[AArch64] Improve v8.1-A code-gen for atomic load-and
2018-02-12 17:03:11 +00:00
AArch64InstrFormats.td
[AArch64][SVE] Asm: Support for LD1R load-and-replicate scalar instructions.
2018-05-08 10:46:55 +00:00
AArch64InstrInfo.cpp
[DebugInfo] Examine all uses of isDebugValue() for debug instructions.
2018-05-09 02:42:00 +00:00
AArch64InstrInfo.h
Remove \brief commands from doxygen comments.
2018-05-01 15:54:18 +00:00
AArch64InstrInfo.td
[AArch64] Improve single vector lane stores
2018-05-14 15:26:35 +00:00
AArch64InstructionSelector.cpp
Rename DEBUG macro to LLVM_DEBUG.
2018-05-14 12:53:11 +00:00
AArch64ISelDAGToDAG.cpp
Rename DEBUG macro to LLVM_DEBUG.
2018-05-14 12:53:11 +00:00
AArch64ISelLowering.cpp
Rename DEBUG macro to LLVM_DEBUG.
2018-05-14 12:53:11 +00:00
AArch64ISelLowering.h
[CGP] Split large data structres to sink more GEPs
2018-05-10 18:27:36 +00:00
AArch64LegalizerInfo.cpp
[globalisel] Update GlobalISel emitter to match new representation of extending loads
2018-05-05 20:53:24 +00:00
AArch64LegalizerInfo.h
[aarch64][globalisel] Define G_ATOMIC_CMPXCHG and G_ATOMICRMW_* and make them legal
2017-11-28 20:21:15 +00:00
AArch64LoadStoreOptimizer.cpp
Rename DEBUG macro to LLVM_DEBUG.
2018-05-14 12:53:11 +00:00
AArch64MachineFunctionInfo.h
Remove \brief commands from doxygen comments.
2018-05-01 15:54:18 +00:00
AArch64MacroFusion.cpp
Remove \brief commands from doxygen comments.
2018-05-01 15:54:18 +00:00
AArch64MacroFusion.h
Recommit rL305677: [CodeGen] Add generic MacroFusion pass
2017-06-19 12:53:31 +00:00
AArch64MCInstLower.cpp
Move TargetLoweringObjectFile from CodeGen to Target to fix layering
2018-03-23 23:58:19 +00:00
AArch64MCInstLower.h
[COFF, ARM64] Add support for Windows ARM64 COFF format
2017-06-27 23:58:19 +00:00
AArch64PBQPRegAlloc.cpp
Rename DEBUG macro to LLVM_DEBUG.
2018-05-14 12:53:11 +00:00
AArch64PBQPRegAlloc.h
[CodeGen] Fix some Clang-tidy modernize-use-using and Include What You Use warnings; other minor fixes (NFC).
2017-06-01 23:25:02 +00:00
AArch64PerfectShuffle.h
…
AArch64PromoteConstant.cpp
Rename DEBUG macro to LLVM_DEBUG.
2018-05-14 12:53:11 +00:00
AArch64RedundantCopyElimination.cpp
Rename DEBUG macro to LLVM_DEBUG.
2018-05-14 12:53:11 +00:00
AArch64RegisterBankInfo.cpp
[AArch64] Map G_LOAD on FPR when the definition goes to a copy to FPR
2017-11-18 04:28:59 +00:00
AArch64RegisterBankInfo.h
[AArch64][RegisterBankInfo] Add mapping for G_FPEXT.
2017-11-02 23:38:19 +00:00
AArch64RegisterBanks.td
[aarch64][globalisel] Register banks and classes should have distinct names.
2017-10-18 00:12:43 +00:00
AArch64RegisterInfo.cpp
AArch64: Implement support for the shadowcallstack attribute.
2018-04-04 21:55:44 +00:00
AArch64RegisterInfo.h
[AArch64] Implement dynamic stack probing for windows
2018-02-17 14:26:32 +00:00
AArch64RegisterInfo.td
[AArch64] Disallow vector operand if FPR128 Q register is required.
2018-05-08 10:01:04 +00:00
AArch64SchedA53.td
[AArch64] Clean-up a few over-eager regexps in models.
2018-03-23 11:00:42 +00:00
AArch64SchedA57.td
[AArch64][SVE] Asm: Set SVE as unsupported feature for existing scheduler models.
2017-11-07 15:03:11 +00:00
AArch64SchedA57WriteRes.td
[AArch64] Cortex-A57 FDIV/FSQRT scheduling fix (W-unit)
2016-12-23 12:51:41 +00:00
AArch64SchedCyclone.td
[AArch64][SVE] Asm: Set SVE as unsupported feature for existing scheduler models.
2017-11-07 15:03:11 +00:00
AArch64SchedExynosM1.td
[AArch64][NFC] Make all ProcResource definitions include their SchedModel.
2018-02-01 12:12:01 +00:00
AArch64SchedExynosM3.td
[AArch64] Adjust the cost model for Exynos M3
2018-04-03 22:57:17 +00:00
AArch64SchedFalkor.td
[TableGen] When trying to reuse a scheduler class for instructions from an InstRW, make sure we haven't already seen another InstRW containing this instruction on this CPU.
2018-03-18 19:56:15 +00:00
AArch64SchedFalkorDetails.td
[AArch64][Falkor] Correct load/store increment scheduling details
2018-03-20 13:46:35 +00:00
AArch64SchedKryo.td
[TableGen] When trying to reuse a scheduler class for instructions from an InstRW, make sure we haven't already seen another InstRW containing this instruction on this CPU.
2018-03-18 19:56:15 +00:00
AArch64SchedKryoDetails.td
[AArch64][Kryo] Add missing write latency for LDAXP, LDXP second destination.
2017-06-19 21:57:42 +00:00
AArch64SchedThunderX2T99.td
[AArch64] Clean-up a few over-eager regexps in models.
2018-03-23 11:00:42 +00:00
AArch64SchedThunderX.td
[TableGen] When trying to reuse a scheduler class for instructions from an InstRW, make sure we haven't already seen another InstRW containing this instruction on this CPU.
2018-03-18 19:56:15 +00:00
AArch64Schedule.td
CodeGen: Use MachineInstr& in TargetInstrInfo, NFC
2016-06-30 00:01:54 +00:00
AArch64SelectionDAGInfo.cpp
AArch64/X86: Factor out common bzero logic; NFC
2017-12-18 23:14:28 +00:00
AArch64SelectionDAGInfo.h
Pass DebugLoc and SDLoc by const ref.
2016-06-12 15:39:02 +00:00
AArch64SIMDInstrOpt.cpp
[TargetSchedule] shrink interface for init(); NFCI
2018-04-08 19:56:04 +00:00
AArch64StorePairSuppress.cpp
Rename DEBUG macro to LLVM_DEBUG.
2018-05-14 12:53:11 +00:00
AArch64Subtarget.cpp
AArch64: Implement support for the shadowcallstack attribute.
2018-04-04 21:55:44 +00:00
AArch64Subtarget.h
Remove \brief commands from doxygen comments.
2018-05-01 15:54:18 +00:00
AArch64SVEInstrInfo.td
[AArch64][SVE] Asm: Support for LD1R load-and-replicate scalar instructions.
2018-05-08 10:46:55 +00:00
AArch64SystemOperands.td
[AArch64][SVE] Extend parsing of Prefetch operation for SVE.
2018-05-14 11:54:41 +00:00
AArch64TargetMachine.cpp
Revert r331816 and r331820 - [globalisel] Add a combiner helpers for extending loads and use them in a pre-legalize combiner for AArch64
2018-05-09 05:00:17 +00:00
AArch64TargetMachine.h
(Re-landing) Expose a TargetMachine::getTargetTransformInfo function
2017-12-22 18:21:59 +00:00
AArch64TargetObjectFile.cpp
Move Object format code to lib/BinaryFormat.
2017-06-07 03:48:56 +00:00
AArch64TargetObjectFile.h
Move TargetLoweringObjectFile from CodeGen to Target to fix layering
2018-03-23 23:58:19 +00:00
AArch64TargetTransformInfo.cpp
Rename DEBUG macro to LLVM_DEBUG.
2018-05-14 12:53:11 +00:00
AArch64TargetTransformInfo.h
[TTI, AArch64] Add transpose shuffle kind
2018-04-26 13:48:33 +00:00
CMakeLists.txt
Revert r331816 and r331820 - [globalisel] Add a combiner helpers for extending loads and use them in a pre-legalize combiner for AArch64
2018-05-09 05:00:17 +00:00
LLVMBuild.txt
…
SVEInstrFormats.td
[AArch64][SVE] Extend parsing of Prefetch operation for SVE.
2018-05-14 11:54:41 +00:00