229ab5aa2b
This prevents cases where some of the operands match from hitting verifier errors with kill flags. These nodes should have been removed earlier in most cases. Fixes the direct issue from #149380. #151855 cleans up the codegen.
119 lines
5.1 KiB
YAML
119 lines
5.1 KiB
YAML
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 5
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# RUN: llc -mtriple=aarch64-none-linux-gnu -run-pass aarch64-expand-pseudo -verify-machineinstrs %s -o - | FileCheck %s
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---
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name: BSL_COPY
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tracksRegLiveness: true
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body: |
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bb.0.entry:
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liveins: $q20, $q21, $q22, $q23, $q6, $q1, $q7
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; CHECK-LABEL: name: BSL_COPY
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; CHECK: liveins: $q20, $q21, $q22, $q23, $q6, $q1, $q7
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: renamable $q2 = ORRv16i8 killed renamable $q20, killed renamable $q20
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; CHECK-NEXT: renamable $q2 = BSLv16i8 killed renamable $q2, renamable $q21, renamable $q6, implicit killed $q21_q22_q23, implicit killed $q0_q1_q2_q3, implicit-def $q0_q1_q2_q3
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; CHECK-NEXT: $q22 = ORRv16i8 $q0, killed $q0
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; CHECK-NEXT: $q23 = ORRv16i8 $q1, killed $q1
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; CHECK-NEXT: $q24 = ORRv16i8 $q2, killed $q2
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; CHECK-NEXT: $q25 = ORRv16i8 $q3, killed $q3
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; CHECK-NEXT: RET undef $lr, implicit $q22
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renamable $q2 = BSPv16i8 killed renamable $q20, renamable $q21, renamable $q6, implicit killed $q21_q22_q23, implicit killed $q0_q1_q2_q3, implicit-def $q0_q1_q2_q3
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$q22 = ORRv16i8 $q0, killed $q0
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$q23 = ORRv16i8 $q1, killed $q1
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$q24 = ORRv16i8 $q2, killed $q2
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$q25 = ORRv16i8 $q3, killed $q3
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RET_ReallyLR implicit $q22
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...
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---
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name: BSL
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tracksRegLiveness: true
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body: |
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bb.0.entry:
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liveins: $q20, $q21, $q22, $q23, $q6, $q1, $q7
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; CHECK-LABEL: name: BSL
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; CHECK: liveins: $q20, $q21, $q22, $q23, $q6, $q1, $q7
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: renamable $q2 = BSLv16i8 killed renamable $q2, renamable $q21, renamable $q6, implicit killed $q21_q22_q23, implicit killed $q0_q1_q2_q3, implicit-def $q0_q1_q2_q3
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; CHECK-NEXT: $q22 = ORRv16i8 $q0, killed $q0
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; CHECK-NEXT: $q23 = ORRv16i8 $q1, killed $q1
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; CHECK-NEXT: $q24 = ORRv16i8 $q2, killed $q2
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; CHECK-NEXT: $q25 = ORRv16i8 $q3, killed $q3
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; CHECK-NEXT: RET undef $lr, implicit $q22
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renamable $q2 = BSPv16i8 killed renamable $q2, renamable $q21, renamable $q6, implicit killed $q21_q22_q23, implicit killed $q0_q1_q2_q3, implicit-def $q0_q1_q2_q3
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$q22 = ORRv16i8 $q0, killed $q0
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$q23 = ORRv16i8 $q1, killed $q1
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$q24 = ORRv16i8 $q2, killed $q2
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$q25 = ORRv16i8 $q3, killed $q3
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RET_ReallyLR implicit $q22
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...
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---
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name: BIF
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tracksRegLiveness: true
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body: |
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bb.0.entry:
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liveins: $q20, $q21, $q22, $q23, $q6, $q1, $q7
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; CHECK-LABEL: name: BIF
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; CHECK: liveins: $q20, $q21, $q22, $q23, $q6, $q1, $q7
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: renamable $q2 = BIFv16i8 renamable $q2, renamable $q6, killed renamable $q20, implicit killed $q21_q22_q23, implicit killed $q0_q1_q2_q3, implicit-def $q0_q1_q2_q3
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; CHECK-NEXT: $q22 = ORRv16i8 $q0, killed $q0
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; CHECK-NEXT: $q23 = ORRv16i8 $q1, killed $q1
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; CHECK-NEXT: $q24 = ORRv16i8 $q2, killed $q2
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; CHECK-NEXT: $q25 = ORRv16i8 $q3, killed $q3
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; CHECK-NEXT: RET undef $lr, implicit $q22
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renamable $q2 = BSPv16i8 killed renamable $q20, renamable $q2, renamable $q6, implicit killed $q21_q22_q23, implicit killed $q0_q1_q2_q3, implicit-def $q0_q1_q2_q3
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$q22 = ORRv16i8 $q0, killed $q0
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$q23 = ORRv16i8 $q1, killed $q1
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$q24 = ORRv16i8 $q2, killed $q2
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$q25 = ORRv16i8 $q3, killed $q3
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RET_ReallyLR implicit $q22
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...
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---
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name: BIT
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tracksRegLiveness: true
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body: |
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bb.0.entry:
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liveins: $q20, $q21, $q22, $q23, $q6, $q1, $q7
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; CHECK-LABEL: name: BIT
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; CHECK: liveins: $q20, $q21, $q22, $q23, $q6, $q1, $q7
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: renamable $q2 = BITv16i8 renamable $q2, renamable $q21, killed renamable $q20, implicit killed $q21_q22_q23, implicit killed $q0_q1_q2_q3, implicit-def $q0_q1_q2_q3
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; CHECK-NEXT: $q22 = ORRv16i8 $q0, killed $q0
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; CHECK-NEXT: $q23 = ORRv16i8 $q1, killed $q1
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; CHECK-NEXT: $q24 = ORRv16i8 $q2, killed $q2
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; CHECK-NEXT: $q25 = ORRv16i8 $q3, killed $q3
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; CHECK-NEXT: RET undef $lr, implicit $q22
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renamable $q2 = BSPv16i8 killed renamable $q20, renamable $q21, renamable $q2, implicit killed $q21_q22_q23, implicit killed $q0_q1_q2_q3, implicit-def $q0_q1_q2_q3
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$q22 = ORRv16i8 $q0, killed $q0
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$q23 = ORRv16i8 $q1, killed $q1
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$q24 = ORRv16i8 $q2, killed $q2
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$q25 = ORRv16i8 $q3, killed $q3
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RET_ReallyLR implicit $q22
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...
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---
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name: DoubleOp
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tracksRegLiveness: true
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body: |
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bb.0.entry:
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liveins: $q2
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; CHECK-LABEL: name: DoubleOp
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; CHECK: liveins: $q2
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: renamable $q0 = MOVIv8i16 1, 0
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; CHECK-NEXT: renamable $q1 = ORRv16i8 renamable $q2, renamable $q2
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; CHECK-NEXT: renamable $q1 = BSLv16i8 killed renamable $q1, renamable $q2, renamable $q0
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; CHECK-NEXT: renamable $q0 = SQADDv8i16 killed renamable $q1, killed renamable $q0
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; CHECK-NEXT: RET undef $lr, implicit $q0
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renamable $q0 = MOVIv8i16 1, 0
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renamable $q1 = BSPv16i8 killed renamable $q2, renamable $q2, renamable $q0
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renamable $q0 = SQADDv8i16 killed renamable $q1, killed renamable $q0
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RET_ReallyLR implicit $q0
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...
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