44556e64f2
This intrinsic is meant to be used in functions that have a "tail" that needs to be run with all the lanes enabled. The "tail" may contain complex control flow that makes it unsuitable for the use of the existing WWM intrinsics. Instead, we will pretend that the function starts with all the lanes enabled, then branches into the actual body of the function for the lanes that were meant to run it, and then finally all the lanes will rejoin and run the tail. As such, the intrinsic will return the EXEC mask for the body of the function, and is meant to be used only as part of a very limited pattern (for now only in amdgpu_cs_chain functions): ``` entry: %func_exec = call i1 @llvm.amdgcn.init.whole.wave() br i1 %func_exec, label %func, label %tail func: ; ... stuff that should run with the actual EXEC mask br label %tail tail: ; ... stuff that runs with all the lanes enabled; ; can contain more than one basic block ``` It's an error to use the result of this intrinsic for anything other than a branch (but unfortunately checking that in the verifier is non-trivial because SIAnnotateControlFlow will introduce an amdgcn.if between the intrinsic and the branch). The intrinsic is lowered to a SI_INIT_WHOLE_WAVE pseudo, which for now is expanded in si-wqm (which is where SI_INIT_EXEC is handled too); however the information that the function was conceptually started in whole wave mode is stored in the machine function info (hasInitWholeWave). This will be useful in prolog epilog insertion, where we can skip saving the inactive lanes for CSRs (since if the function started with all the lanes active, then there are no inactive lanes to preserve).
138 lines
4.0 KiB
C++
138 lines
4.0 KiB
C++
//===-- AMDGPUMachineFunctionInfo.h -------------------------------*- C++ -*-=//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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#ifndef LLVM_LIB_TARGET_AMDGPU_AMDGPUMACHINEFUNCTION_H
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#define LLVM_LIB_TARGET_AMDGPU_AMDGPUMACHINEFUNCTION_H
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#include "Utils/AMDGPUBaseInfo.h"
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#include "llvm/ADT/DenseMap.h"
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#include "llvm/CodeGen/MachineFunction.h"
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#include "llvm/IR/DataLayout.h"
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#include "llvm/IR/Function.h"
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#include "llvm/IR/GlobalValue.h"
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#include "llvm/IR/GlobalVariable.h"
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namespace llvm {
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class AMDGPUSubtarget;
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class AMDGPUMachineFunction : public MachineFunctionInfo {
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/// A map to keep track of local memory objects and their offsets within the
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/// local memory space.
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SmallDenseMap<const GlobalValue *, unsigned, 4> LocalMemoryObjects;
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protected:
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uint64_t ExplicitKernArgSize = 0; // Cache for this.
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Align MaxKernArgAlign; // Cache for this.
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/// Number of bytes in the LDS that are being used.
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uint32_t LDSSize = 0;
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uint32_t GDSSize = 0;
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/// Number of bytes in the LDS allocated statically. This field is only used
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/// in the instruction selector and not part of the machine function info.
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uint32_t StaticLDSSize = 0;
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uint32_t StaticGDSSize = 0;
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/// Align for dynamic shared memory if any. Dynamic shared memory is
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/// allocated directly after the static one, i.e., LDSSize. Need to pad
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/// LDSSize to ensure that dynamic one is aligned accordingly.
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/// The maximal alignment is updated during IR translation or lowering
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/// stages.
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Align DynLDSAlign;
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// Flag to check dynamic LDS usage by kernel.
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bool UsesDynamicLDS = false;
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// Kernels + shaders. i.e. functions called by the hardware and not called
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// by other functions.
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bool IsEntryFunction = false;
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// Entry points called by other functions instead of directly by the hardware.
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bool IsModuleEntryFunction = false;
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// Functions with the amdgpu_cs_chain or amdgpu_cs_chain_preserve CC.
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bool IsChainFunction = false;
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bool NoSignedZerosFPMath = false;
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// Function may be memory bound.
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bool MemoryBound = false;
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// Kernel may need limited waves per EU for better performance.
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bool WaveLimiter = false;
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bool HasInitWholeWave = false;
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public:
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AMDGPUMachineFunction(const Function &F, const AMDGPUSubtarget &ST);
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uint64_t getExplicitKernArgSize() const {
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return ExplicitKernArgSize;
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}
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Align getMaxKernArgAlign() const { return MaxKernArgAlign; }
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uint32_t getLDSSize() const {
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return LDSSize;
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}
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uint32_t getGDSSize() const {
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return GDSSize;
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}
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bool isEntryFunction() const {
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return IsEntryFunction;
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}
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bool isModuleEntryFunction() const { return IsModuleEntryFunction; }
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bool isChainFunction() const { return IsChainFunction; }
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// The stack is empty upon entry to this function.
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bool isBottomOfStack() const {
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return isEntryFunction() || isChainFunction();
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}
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bool hasNoSignedZerosFPMath() const {
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return NoSignedZerosFPMath;
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}
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bool isMemoryBound() const {
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return MemoryBound;
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}
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bool needsWaveLimiter() const {
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return WaveLimiter;
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}
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bool hasInitWholeWave() const { return HasInitWholeWave; }
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void setInitWholeWave() { HasInitWholeWave = true; }
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unsigned allocateLDSGlobal(const DataLayout &DL, const GlobalVariable &GV) {
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return allocateLDSGlobal(DL, GV, DynLDSAlign);
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}
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unsigned allocateLDSGlobal(const DataLayout &DL, const GlobalVariable &GV,
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Align Trailing);
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static std::optional<uint32_t> getLDSKernelIdMetadata(const Function &F);
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static std::optional<uint32_t> getLDSAbsoluteAddress(const GlobalValue &GV);
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Align getDynLDSAlign() const { return DynLDSAlign; }
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void setDynLDSAlign(const Function &F, const GlobalVariable &GV);
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void setUsesDynamicLDS(bool DynLDS);
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bool isDynamicLDSUsed() const;
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};
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}
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#endif
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