08dd645c15
When we are using the Zcmp extension together with the E extension in 32-bit mode and we need to spill both callee-saved registers as well as needing a couple of 32-bit stack slots, we emit a meaningless stack adjustment with cm.push/cm.popret. Furthermore this leads to the stack slot for the ra being clobbered so control returns to a random location. This is just a pre-commit test so that the PR for the fix shows the difference in code generation.
50 lines
1.8 KiB
LLVM
50 lines
1.8 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 4
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; RUN: llc -mtriple=riscv32 -mattr=+zcmp,+e -target-abi ilp32e -verify-machineinstrs < %s | FileCheck %s --check-prefix=RV32
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define ptr @func(ptr %s, i32 %_c, ptr %incdec.ptr, i1 %0, i8 %conv14) #0 {
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; RV32-LABEL: func:
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; RV32: # %bb.0: # %entry
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; RV32-NEXT: cm.push {ra, s0-s1}, -24
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; RV32-NEXT: .cfi_def_cfa_offset 24
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; RV32-NEXT: .cfi_offset ra, -12
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; RV32-NEXT: .cfi_offset s0, -8
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; RV32-NEXT: .cfi_offset s1, -4
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; RV32-NEXT: sw a4, 4(sp) # 4-byte Folded Spill
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; RV32-NEXT: sw a2, 0(sp) # 4-byte Folded Spill
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; RV32-NEXT: mv a2, a1
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; RV32-NEXT: mv s1, a0
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; RV32-NEXT: li a0, 1
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; RV32-NEXT: andi a3, a3, 1
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; RV32-NEXT: .LBB0_1: # %while.body
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; RV32-NEXT: # =>This Inner Loop Header: Depth=1
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; RV32-NEXT: mv s0, a0
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; RV32-NEXT: li a0, 0
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; RV32-NEXT: bnez a3, .LBB0_1
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; RV32-NEXT: # %bb.2: # %while.end
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; RV32-NEXT: lui a0, 4112
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; RV32-NEXT: addi a1, a0, 257
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; RV32-NEXT: mv a0, a2
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; RV32-NEXT: call __mulsi3
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; RV32-NEXT: sw a0, 0(zero)
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; RV32-NEXT: andi s0, s0, 1
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; RV32-NEXT: lw a0, 0(sp) # 4-byte Folded Reload
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; RV32-NEXT: add s0, s0, a0
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; RV32-NEXT: lw a0, 4(sp) # 4-byte Folded Reload
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; RV32-NEXT: sb a0, 0(s0)
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; RV32-NEXT: mv a0, s1
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; RV32-NEXT: cm.popret {ra, s0-s1}, 24
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entry:
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br label %while.body
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while.body: ; preds = %while.body, %entry
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%n.addr.042 = phi i32 [ 1, %entry ], [ 0, %while.body ]
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br i1 %0, label %while.body, label %while.end
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while.end: ; preds = %while.body
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%or5 = mul i32 %_c, 16843009
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store i32 %or5, ptr null, align 4
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%1 = and i32 %n.addr.042, 1
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%scevgep = getelementptr i8, ptr %incdec.ptr, i32 %1
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store i8 %conv14, ptr %scevgep, align 1
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ret ptr %s
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}
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