This reverts commit 2bd369b48dbf0bc3128becb7ef8f8a1b82514b87.
That commit triggered failed assertions:
$ cat repro.c
short *a;
int b;
void h() {
short *c = a;
b = 0;
for (; b < 4; b++) {
unsigned d = a[b] + a[b + 4 * 2], e = a[b] - a[b + 4 * 2],
f = (a[b + 4] >> 1) - a[b + 4 * 3],
g = a[b + 4] + (a[b + 4 * 3] >> 1);
c[b] = g;
c[b + 4] = e + f;
c[b + 4 * 2] = e - f;
c[b + 4 * 3] = d - g;
}
}
$ clang -target aarch64-linux-gnu -c -O2 repro.c
clang: ../lib/Transforms/Vectorize/SLPVectorizer.cpp:12503: llvm::Value* llvm::slpvectorizer::BoUpSLP::vectorizeTree(llvm::slpvectorizer::BoUpSLP::TreeEntry*, bool): Assertion `(MinBWs.contains(getOperandEntry(E, 0)) || MinBWs.contains(getOperandEntry(E, 1))) && "Expected item in MinBWs."' failed.
36 lines
1.5 KiB
LLVM
36 lines
1.5 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
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; RUN: opt -S -passes=slp-vectorizer < %s | FileCheck %s
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define i32 @alt_cmp(i16 %call46) {
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; CHECK-LABEL: @alt_cmp(
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; CHECK-NEXT: entry:
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; CHECK-NEXT: [[CALL47:%.*]] = tail call i16 null(i16 0)
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; CHECK-NEXT: [[TMP0:%.*]] = insertelement <4 x i16> <i16 0, i16 poison, i16 0, i16 0>, i16 [[CALL46:%.*]], i32 1
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; CHECK-NEXT: [[TMP1:%.*]] = insertelement <4 x i16> <i16 0, i16 poison, i16 0, i16 0>, i16 [[CALL47]], i32 1
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; CHECK-NEXT: [[TMP2:%.*]] = icmp ult <4 x i16> [[TMP0]], [[TMP1]]
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; CHECK-NEXT: [[TMP3:%.*]] = icmp ugt <4 x i16> [[TMP0]], [[TMP1]]
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; CHECK-NEXT: [[TMP4:%.*]] = shufflevector <4 x i1> [[TMP2]], <4 x i1> [[TMP3]], <4 x i32> <i32 0, i32 5, i32 2, i32 3>
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; CHECK-NEXT: [[TMP5:%.*]] = zext <4 x i1> [[TMP4]] to <4 x i16>
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; CHECK-NEXT: [[TMP6:%.*]] = call i16 @llvm.vector.reduce.or.v4i16(<4 x i16> [[TMP5]])
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; CHECK-NEXT: [[OP_RDX:%.*]] = or i16 [[TMP6]], 0
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; CHECK-NEXT: [[EXT:%.*]] = zext i16 [[OP_RDX]] to i32
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; CHECK-NEXT: ret i32 [[EXT]]
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;
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entry:
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%0 = icmp ult i16 0, 0
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%cond40 = zext i1 %0 to i16
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%add41 = or i16 0, %cond40
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%call47 = tail call i16 null(i16 0)
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%.not299 = icmp ugt i16 %call46, %call47
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%cond60 = zext i1 %.not299 to i16
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%add61 = or i16 %add41, %cond60
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%1 = icmp ugt i16 0, 0
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%cond76 = zext i1 %1 to i16
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%add77 = or i16 %add61, %cond76
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%2 = icmp ult i16 0, 0
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%cond144 = zext i1 %2 to i16
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%add145 = or i16 %add77, %cond144
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%ext = zext i16 %add145 to i32
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ret i32 %ext
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}
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