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llvm-project/llvm/test/CodeGen/MIR
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Alex MacLean b44c50d416
[NVPTX] Rework and cleanup FTZ ISel (#146410) 
This change cleans up DAG-to-DAG instruction selection around FTZ and
SETP comparison mode. Largely these changes do not impact functionality
though support for `{sin.cos}.approx.ftz.f32` is added.
2025-07-09 11:16:48 -07:00
..
AArch64
[AArch64] Correct position of CFI Instruction for Pointer Authentication (#137795)
2025-05-06 11:31:04 +02:00
AMDGPU
[AMDGPU] Replace dynamic VGPR feature with attribute (#133444)
2025-06-24 11:09:36 +02:00
ARM
…
Generic
MIR: Replace undef with poison in some MIR tests (#131282)
2025-03-15 00:20:18 +07:00
Hexagon
[win] NFC: Rename EHCatchret to EHCont to allow for EH Continuation targets that aren't catchret instructions (#129953)
2025-03-06 09:28:44 -08:00
Mips
[test] Change llc -march=mips* to -mtriple=mips*
2024-12-10 22:14:06 -08:00
NVPTX
[NVPTX] Rework and cleanup FTZ ISel (#146410)
2025-07-09 11:16:48 -07:00
PowerPC
MIR: Replace undef with poison in some MIR tests (#131282)
2025-03-15 00:20:18 +07:00
RISCV
…
WebAssembly
…
X86
[Verifier] Require that dbg.declare variable is a ptr (#134355)
2025-04-04 15:34:45 +02:00
README
…

README 

This directory contains tests for the MIR file format parser and printer. It
was necessary to split the tests across different targets as no single target
covers all features available in machine IR.

Tests for codegen passes should NOT be here but in test/CodeGen/sometarget. As
a rule of thumb this directory should only contain tests using
'llc -run-pass none'.