f3520c538d
This changes the branch condition to use the AVL's backedge value instead of the EVL-based IV. This allows us to emit bnez on RISC-V and removes a use of the trip count, which should reduce register pressure. To match phis with VPlanPatternMatch I've had to relax the assert that the number of operands must exactly match the pattern for the Phi opcode, and I've copied over m_ZExtOrSelf from the LLVM IR PatternMatch.h. Fixes #151459
59 lines
3.2 KiB
LLVM
59 lines
3.2 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 5
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; RUN: opt < %s -mtriple=riscv64 -mattr=+v -p loop-vectorize -pass-remarks-analysis=loop-vectorize -S 2>&1 | FileCheck %s
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; CHECK: remark: <unknown>:0:0: the cost-model indicates that interleaving is not beneficial
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define float @s311(float %a_0, float %s311_sum) {
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; CHECK-LABEL: define float @s311(
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; CHECK-SAME: float [[A_0:%.*]], float [[S311_SUM:%.*]]) #[[ATTR0:[0-9]+]] {
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; CHECK-NEXT: [[ENTRY:.*:]]
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; CHECK-NEXT: br i1 false, label %[[SCALAR_PH:.*]], label %[[VECTOR_PH:.*]]
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; CHECK: [[VECTOR_PH]]:
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; CHECK-NEXT: [[BROADCAST_SPLATINSERT:%.*]] = insertelement <vscale x 4 x float> poison, float [[A_0]], i64 0
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; CHECK-NEXT: [[BROADCAST_SPLAT:%.*]] = shufflevector <vscale x 4 x float> [[BROADCAST_SPLATINSERT]], <vscale x 4 x float> poison, <vscale x 4 x i32> zeroinitializer
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; CHECK-NEXT: br label %[[VECTOR_BODY:.*]]
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; CHECK: [[VECTOR_BODY]]:
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; CHECK-NEXT: [[VEC_PHI:%.*]] = phi float [ [[S311_SUM]], %[[VECTOR_PH]] ], [ [[TMP6:%.*]], %[[VECTOR_BODY]] ]
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; CHECK-NEXT: [[AVL:%.*]] = phi i32 [ 1200, %[[VECTOR_PH]] ], [ [[AVL_NEXT:%.*]], %[[VECTOR_BODY]] ]
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; CHECK-NEXT: [[TMP9:%.*]] = call i32 @llvm.experimental.get.vector.length.i32(i32 [[AVL]], i32 4, i1 true)
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; CHECK-NEXT: [[TMP6]] = call float @llvm.vp.reduce.fadd.nxv4f32(float [[VEC_PHI]], <vscale x 4 x float> [[BROADCAST_SPLAT]], <vscale x 4 x i1> splat (i1 true), i32 [[TMP9]])
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; CHECK-NEXT: [[AVL_NEXT]] = sub nuw i32 [[AVL]], [[TMP9]]
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; CHECK-NEXT: [[TMP7:%.*]] = icmp eq i32 [[AVL_NEXT]], 0
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; CHECK-NEXT: br i1 [[TMP7]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP0:![0-9]+]]
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; CHECK: [[MIDDLE_BLOCK]]:
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; CHECK-NEXT: br label %[[EXIT:.*]]
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; CHECK: [[SCALAR_PH]]:
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; CHECK-NEXT: br label %[[LOOP:.*]]
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; CHECK: [[LOOP]]:
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; CHECK-NEXT: [[IV:%.*]] = phi i32 [ 0, %[[SCALAR_PH]] ], [ [[IV_NEXT:%.*]], %[[LOOP]] ]
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; CHECK-NEXT: [[RED:%.*]] = phi float [ [[S311_SUM]], %[[SCALAR_PH]] ], [ [[RED_NEXT:%.*]], %[[LOOP]] ]
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; CHECK-NEXT: [[RED_NEXT]] = fadd float [[A_0]], [[RED]]
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; CHECK-NEXT: [[IV_NEXT]] = add nuw nsw i32 [[IV]], 1
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; CHECK-NEXT: [[EXITCOND:%.*]] = icmp eq i32 [[IV_NEXT]], 1200
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; CHECK-NEXT: br i1 [[EXITCOND]], label %[[EXIT]], label %[[LOOP]], !llvm.loop [[LOOP4:![0-9]+]]
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; CHECK: [[EXIT]]:
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; CHECK-NEXT: [[RED_LCSSA:%.*]] = phi float [ [[RED_NEXT]], %[[LOOP]] ], [ [[TMP6]], %[[MIDDLE_BLOCK]] ]
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; CHECK-NEXT: ret float [[RED_LCSSA]]
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;
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entry:
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br label %loop
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loop:
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%iv = phi i32 [ 0, %entry ], [ %iv.next, %loop ]
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%red = phi float [ %s311_sum, %entry ], [ %red.next, %loop ]
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%red.next = fadd float %a_0, %red
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%iv.next = add nuw nsw i32 %iv, 1
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%exitcond = icmp eq i32 %iv.next, 1200
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br i1 %exitcond, label %exit, label %loop
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exit:
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%red.lcssa = phi float [ %red.next, %loop ]
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ret float %red.lcssa
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}
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;.
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; CHECK: [[LOOP0]] = distinct !{[[LOOP0]], [[META1:![0-9]+]], [[META2:![0-9]+]], [[META3:![0-9]+]]}
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; CHECK: [[META1]] = !{!"llvm.loop.isvectorized", i32 1}
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; CHECK: [[META2]] = !{!"llvm.loop.isvectorized.tailfoldingstyle", !"evl"}
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; CHECK: [[META3]] = !{!"llvm.loop.unroll.runtime.disable"}
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; CHECK: [[LOOP4]] = distinct !{[[LOOP4]], [[META3]], [[META1]]}
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;.
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