300d2c6d20
Move the logic to expand SCEVs directly to a late VPlan transform that expands SCEVs in the entry block. This turns VPExpandSCEVRecipe into an abstract recipe without execute, which clarifies how the recipe is handled, i.e. it is not executed like regular recipes. It also helps to simplify construction, as now scalar evolution isn't required to be passed to the recipe.
347 lines
13 KiB
C++
347 lines
13 KiB
C++
//===- llvm/unittest/Transforms/Vectorize/VPlanHCFGTest.cpp ---------------===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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#include "../lib/Transforms/Vectorize/VPlan.h"
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#include "../lib/Transforms/Vectorize/VPlanTransforms.h"
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#include "VPlanTestBase.h"
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#include "llvm/Analysis/TargetLibraryInfo.h"
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#include "llvm/TargetParser/Triple.h"
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#include "gtest/gtest.h"
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#include <string>
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namespace llvm {
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namespace {
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class VPlanHCFGTest : public VPlanTestIRBase {};
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TEST_F(VPlanHCFGTest, testBuildHCFGInnerLoop) {
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const char *ModuleString =
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"define void @f(ptr %A, i64 %N) {\n"
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"entry:\n"
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" br label %for.body\n"
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"for.body:\n"
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" %indvars.iv = phi i64 [ 0, %entry ], [ %indvars.iv.next, %for.body ]\n"
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" %arr.idx = getelementptr inbounds i32, ptr %A, i64 %indvars.iv\n"
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" %l1 = load i32, ptr %arr.idx, align 4\n"
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" %res = add i32 %l1, 10\n"
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" store i32 %res, ptr %arr.idx, align 4\n"
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" %indvars.iv.next = add i64 %indvars.iv, 1\n"
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" %exitcond = icmp ne i64 %indvars.iv.next, %N\n"
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" br i1 %exitcond, label %for.body, label %for.end\n"
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"for.end:\n"
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" ret void\n"
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"}\n";
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Module &M = parseModule(ModuleString);
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Function *F = M.getFunction("f");
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BasicBlock *LoopHeader = F->getEntryBlock().getSingleSuccessor();
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auto Plan = buildVPlan(LoopHeader);
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VPBasicBlock *Entry = Plan->getEntry()->getEntryBasicBlock();
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EXPECT_EQ(0u, Entry->getNumPredecessors());
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EXPECT_EQ(2u, Entry->getNumSuccessors());
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// Check that the region following the preheader consists of a block for the
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// original header and a separate latch.
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VPBasicBlock *VecBB = Plan->getVectorLoopRegion()->getEntryBasicBlock();
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EXPECT_EQ(11u, VecBB->size());
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EXPECT_EQ(0u, VecBB->getNumPredecessors());
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EXPECT_EQ(0u, VecBB->getNumSuccessors());
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EXPECT_EQ(VecBB->getParent()->getEntryBasicBlock(), VecBB);
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EXPECT_EQ(&*Plan, VecBB->getPlan());
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auto Iter = VecBB->begin();
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auto *CanIV = dyn_cast<VPCanonicalIVPHIRecipe>(&*Iter++);
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EXPECT_NE(nullptr, CanIV);
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auto *Phi = dyn_cast<VPPhi>(&*Iter++);
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EXPECT_NE(nullptr, Phi);
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VPInstruction *Idx = dyn_cast<VPInstruction>(&*Iter++);
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EXPECT_EQ(Instruction::GetElementPtr, Idx->getOpcode());
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EXPECT_EQ(2u, Idx->getNumOperands());
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EXPECT_EQ(Phi, Idx->getOperand(1));
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VPInstruction *Load = dyn_cast<VPInstruction>(&*Iter++);
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EXPECT_EQ(Instruction::Load, Load->getOpcode());
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EXPECT_EQ(1u, Load->getNumOperands());
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EXPECT_EQ(Idx, Load->getOperand(0));
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VPInstruction *Add = dyn_cast<VPInstruction>(&*Iter++);
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EXPECT_EQ(Instruction::Add, Add->getOpcode());
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EXPECT_EQ(2u, Add->getNumOperands());
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EXPECT_EQ(Load, Add->getOperand(0));
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VPInstruction *Store = dyn_cast<VPInstruction>(&*Iter++);
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EXPECT_EQ(Instruction::Store, Store->getOpcode());
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EXPECT_EQ(2u, Store->getNumOperands());
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EXPECT_EQ(Add, Store->getOperand(0));
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EXPECT_EQ(Idx, Store->getOperand(1));
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VPInstruction *IndvarAdd = dyn_cast<VPInstruction>(&*Iter++);
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EXPECT_EQ(Instruction::Add, IndvarAdd->getOpcode());
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EXPECT_EQ(2u, IndvarAdd->getNumOperands());
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EXPECT_EQ(Phi, IndvarAdd->getOperand(0));
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VPInstruction *ICmp = dyn_cast<VPInstruction>(&*Iter++);
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EXPECT_EQ(Instruction::ICmp, ICmp->getOpcode());
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EXPECT_EQ(2u, ICmp->getNumOperands());
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EXPECT_EQ(IndvarAdd, ICmp->getOperand(0));
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#if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
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// Add an external value to check we do not print the list of external values,
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// as this is not required with the new printing.
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Plan->getOrAddLiveIn(&*F->arg_begin());
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std::string FullDump;
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raw_string_ostream OS(FullDump);
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Plan->printDOT(OS);
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const char *ExpectedStr = R"(digraph VPlan {
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graph [labelloc=t, fontsize=30; label="Vectorization Plan\n for UF\>=1\nLive-in vp\<%0\> = VF * UF\nLive-in vp\<%1\> = vector-trip-count\nLive-in ir\<%N\> = original trip-count\n"]
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node [shape=rect, fontname=Courier, fontsize=30]
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edge [fontname=Courier, fontsize=30]
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compound=true
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N0 [label =
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"ir-bb\<entry\>:\l" +
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"Successor(s): scalar.ph, vector.ph\l"
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]
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N0 -> N1 [ label="T"]
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N0 -> N2 [ label="F"]
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N1 [label =
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"scalar.ph:\l" +
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"Successor(s): ir-bb\<for.body\>\l"
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]
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N1 -> N3 [ label=""]
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N3 [label =
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"ir-bb\<for.body\>:\l" +
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" IR %indvars.iv = phi i64 [ 0, %entry ], [ %indvars.iv.next, %for.body ]\l" +
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" IR %arr.idx = getelementptr inbounds i32, ptr %A, i64 %indvars.iv\l" +
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" IR %l1 = load i32, ptr %arr.idx, align 4\l" +
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" IR %res = add i32 %l1, 10\l" +
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" IR store i32 %res, ptr %arr.idx, align 4\l" +
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" IR %indvars.iv.next = add i64 %indvars.iv, 1\l" +
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" IR %exitcond = icmp ne i64 %indvars.iv.next, %N\l" +
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"No successors\l"
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]
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N2 [label =
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"vector.ph:\l" +
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"Successor(s): vector loop\l"
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]
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N2 -> N4 [ label="" lhead=cluster_N5]
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subgraph cluster_N5 {
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fontname=Courier
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label="\<x1\> vector loop"
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N4 [label =
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"vector.body:\l" +
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" EMIT vp\<%2\> = CANONICAL-INDUCTION ir\<0\>, vp\<%index.next\>\l" +
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" EMIT-SCALAR ir\<%indvars.iv\> = phi [ ir\<0\>, vector.ph ], [ ir\<%indvars.iv.next\>, vector.body ]\l" +
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" EMIT ir\<%arr.idx\> = getelementptr ir\<%A\>, ir\<%indvars.iv\>\l" +
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" EMIT ir\<%l1\> = load ir\<%arr.idx\>\l" +
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" EMIT ir\<%res\> = add ir\<%l1\>, ir\<10\>\l" +
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" EMIT store ir\<%res\>, ir\<%arr.idx\>\l" +
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" EMIT ir\<%indvars.iv.next\> = add ir\<%indvars.iv\>, ir\<1\>\l" +
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" EMIT ir\<%exitcond\> = icmp ir\<%indvars.iv.next\>, ir\<%N\>\l" +
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" EMIT vp\<%3\> = not ir\<%exitcond\>\l" +
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" EMIT vp\<%index.next\> = add nuw vp\<%2\>, vp\<%0\>\l" +
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" EMIT branch-on-count vp\<%index.next\>, vp\<%1\>\l" +
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"No successors\l"
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]
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}
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N4 -> N6 [ label="" ltail=cluster_N5]
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N6 [label =
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"middle.block:\l" +
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" EMIT vp\<%cmp.n\> = icmp eq ir\<%N\>, vp\<%1\>\l" +
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" EMIT branch-on-cond vp\<%cmp.n\>\l" +
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"Successor(s): ir-bb\<for.end\>, scalar.ph\l"
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]
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N6 -> N7 [ label="T"]
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N6 -> N1 [ label="F"]
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N7 [label =
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"ir-bb\<for.end\>:\l" +
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"No successors\l"
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]
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}
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)";
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EXPECT_EQ(ExpectedStr, FullDump);
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#endif
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}
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TEST_F(VPlanHCFGTest, testVPInstructionToVPRecipesInner) {
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const char *ModuleString =
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"define void @f(ptr %A, i64 %N) {\n"
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"entry:\n"
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" br label %for.body\n"
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"for.body:\n"
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" %indvars.iv = phi i64 [ 0, %entry ], [ %indvars.iv.next, %for.body ]\n"
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" %arr.idx = getelementptr inbounds i32, ptr %A, i64 %indvars.iv\n"
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" %l1 = load i32, ptr %arr.idx, align 4\n"
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" %res = add i32 %l1, 10\n"
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" store i32 %res, ptr %arr.idx, align 4\n"
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" %indvars.iv.next = add i64 %indvars.iv, 1\n"
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" %exitcond = icmp ne i64 %indvars.iv.next, %N\n"
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" br i1 %exitcond, label %for.body, label %for.end\n"
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"for.end:\n"
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" ret void\n"
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"}\n";
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Module &M = parseModule(ModuleString);
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Function *F = M.getFunction("f");
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BasicBlock *LoopHeader = F->getEntryBlock().getSingleSuccessor();
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auto Plan = buildVPlan(LoopHeader);
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TargetLibraryInfoImpl TLII(M.getTargetTriple());
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TargetLibraryInfo TLI(TLII);
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// Current VPlan construction doesn't add a terminator for top-level loop
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// latches. Add it before running transform.
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cast<VPBasicBlock>(Plan->getVectorLoopRegion()->getExiting())
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->appendRecipe(new VPInstruction(
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VPInstruction::BranchOnCond,
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{Plan->getOrAddLiveIn(ConstantInt::getTrue(F->getContext()))}));
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VPlanTransforms::tryToConvertVPInstructionsToVPRecipes(
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Plan, [](PHINode *P) { return nullptr; }, TLI);
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VPBlockBase *Entry = Plan->getEntry()->getEntryBasicBlock();
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EXPECT_EQ(0u, Entry->getNumPredecessors());
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EXPECT_EQ(2u, Entry->getNumSuccessors());
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// Check that the region following the preheader consists of a block for the
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// original header and a separate latch.
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VPBasicBlock *VecBB = Plan->getVectorLoopRegion()->getEntryBasicBlock();
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EXPECT_EQ(12u, VecBB->size());
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EXPECT_EQ(0u, VecBB->getNumPredecessors());
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EXPECT_EQ(0u, VecBB->getNumSuccessors());
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EXPECT_EQ(VecBB->getParent()->getEntryBasicBlock(), VecBB);
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auto Iter = VecBB->begin();
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EXPECT_NE(nullptr, dyn_cast<VPCanonicalIVPHIRecipe>(&*Iter++));
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EXPECT_NE(nullptr, dyn_cast<VPWidenPHIRecipe>(&*Iter++));
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EXPECT_NE(nullptr, dyn_cast<VPWidenGEPRecipe>(&*Iter++));
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EXPECT_NE(nullptr, dyn_cast<VPWidenMemoryRecipe>(&*Iter++));
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EXPECT_NE(nullptr, dyn_cast<VPWidenRecipe>(&*Iter++));
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EXPECT_NE(nullptr, dyn_cast<VPWidenMemoryRecipe>(&*Iter++));
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EXPECT_NE(nullptr, dyn_cast<VPWidenRecipe>(&*Iter++));
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EXPECT_NE(nullptr, dyn_cast<VPWidenRecipe>(&*Iter++));
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EXPECT_NE(nullptr, dyn_cast<VPInstruction>(&*Iter++));
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EXPECT_NE(nullptr, dyn_cast<VPInstruction>(&*Iter++));
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EXPECT_NE(nullptr, dyn_cast<VPInstruction>(&*Iter++));
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EXPECT_NE(nullptr, dyn_cast<VPInstruction>(&*Iter++));
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EXPECT_EQ(VecBB->end(), Iter);
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}
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TEST_F(VPlanHCFGTest, testBuildHCFGInnerLoopMultiExit) {
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const char *ModuleString =
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"define void @f(ptr %A, i64 %N) {\n"
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"entry:\n"
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" br label %loop.header\n"
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"loop.header:\n"
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" %iv = phi i64 [ 0, %entry ], [ %iv.next, %loop.latch ]\n"
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" %arr.idx = getelementptr inbounds i32, ptr %A, i64 %iv\n"
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" %l1 = load i32, ptr %arr.idx, align 4\n"
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" %c = icmp eq i32 %l1, 0\n"
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" br i1 %c, label %exit.1, label %loop.latch\n"
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"loop.latch:\n"
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" %res = add i32 %l1, 10\n"
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" store i32 %res, ptr %arr.idx, align 4\n"
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" %iv.next = add i64 %iv, 1\n"
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" %exitcond = icmp ne i64 %iv.next, %N\n"
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" br i1 %exitcond, label %loop.header, label %exit.2\n"
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"exit.1:\n"
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" ret void\n"
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"exit.2:\n"
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" ret void\n"
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"}\n";
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Module &M = parseModule(ModuleString);
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Function *F = M.getFunction("f");
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BasicBlock *LoopHeader = F->getEntryBlock().getSingleSuccessor();
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auto Plan = buildVPlan(LoopHeader);
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#if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
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// Add an external value to check we do not print the list of external values,
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// as this is not required with the new printing.
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Plan->getOrAddLiveIn(&*F->arg_begin());
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std::string FullDump;
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raw_string_ostream OS(FullDump);
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Plan->printDOT(OS);
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const char *ExpectedStr = R"(digraph VPlan {
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graph [labelloc=t, fontsize=30; label="Vectorization Plan\n for UF\>=1\nLive-in vp\<%0\> = VF * UF\nLive-in vp\<%1\> = vector-trip-count\nLive-in ir\<%N\> = original trip-count\n"]
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node [shape=rect, fontname=Courier, fontsize=30]
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edge [fontname=Courier, fontsize=30]
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compound=true
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N0 [label =
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"ir-bb\<entry\>:\l" +
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"Successor(s): scalar.ph, vector.ph\l"
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]
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N0 -> N1 [ label="T"]
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N0 -> N2 [ label="F"]
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N1 [label =
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"scalar.ph:\l" +
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"Successor(s): ir-bb\<loop.header\>\l"
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]
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N1 -> N3 [ label=""]
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N3 [label =
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"ir-bb\<loop.header\>:\l" +
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" IR %iv = phi i64 [ 0, %entry ], [ %iv.next, %loop.latch ]\l" +
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" IR %arr.idx = getelementptr inbounds i32, ptr %A, i64 %iv\l" +
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" IR %l1 = load i32, ptr %arr.idx, align 4\l" +
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" IR %c = icmp eq i32 %l1, 0\l" +
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"No successors\l"
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]
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N2 [label =
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"vector.ph:\l" +
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"Successor(s): vector loop\l"
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]
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N2 -> N4 [ label="" lhead=cluster_N5]
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subgraph cluster_N5 {
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fontname=Courier
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label="\<x1\> vector loop"
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N4 [label =
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"vector.body:\l" +
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" EMIT vp\<%2\> = CANONICAL-INDUCTION ir\<0\>, vp\<%index.next\>\l" +
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" EMIT-SCALAR ir\<%iv\> = phi [ ir\<0\>, vector.ph ], [ ir\<%iv.next\>, loop.latch ]\l" +
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" EMIT ir\<%arr.idx\> = getelementptr ir\<%A\>, ir\<%iv\>\l" +
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" EMIT ir\<%l1\> = load ir\<%arr.idx\>\l" +
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" EMIT ir\<%c\> = icmp ir\<%l1\>, ir\<0\>\l" +
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"Successor(s): loop.latch\l"
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]
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N4 -> N6 [ label=""]
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N6 [label =
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"loop.latch:\l" +
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" EMIT ir\<%res\> = add ir\<%l1\>, ir\<10\>\l" +
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" EMIT store ir\<%res\>, ir\<%arr.idx\>\l" +
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" EMIT ir\<%iv.next\> = add ir\<%iv\>, ir\<1\>\l" +
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" EMIT ir\<%exitcond\> = icmp ir\<%iv.next\>, ir\<%N\>\l" +
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" EMIT vp\<%3\> = not ir\<%exitcond\>\l" +
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" EMIT vp\<%index.next\> = add nuw vp\<%2\>, vp\<%0\>\l" +
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" EMIT branch-on-count vp\<%index.next\>, vp\<%1\>\l" +
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"No successors\l"
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]
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}
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N6 -> N7 [ label="" ltail=cluster_N5]
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N7 [label =
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"middle.block:\l" +
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" EMIT vp\<%cmp.n\> = icmp eq ir\<%N\>, vp\<%1\>\l" +
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" EMIT branch-on-cond vp\<%cmp.n\>\l" +
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"Successor(s): ir-bb\<exit.2\>, scalar.ph\l"
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]
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N7 -> N8 [ label="T"]
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N7 -> N1 [ label="F"]
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N8 [label =
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"ir-bb\<exit.2\>:\l" +
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"No successors\l"
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]
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}
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)";
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EXPECT_EQ(ExpectedStr, FullDump);
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#endif
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}
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} // namespace
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} // namespace llvm
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