74e8f29f31
`weightCalcHelper` is responsible for adding hints to MRI. Prior to this PR, we fell back on register ID as the last tie breaker for sorting hints. However, there is an opportunity to add an additional sorting characteristic: whether or not a register is a callee-saved-register. I thought of this idea because I saw that `AllocationOrder::create` calls `RegisterClassInfo::getOrder`, which returns a list of registers such that the registers which alias callee-saved-registers come last. From this, I conclude that the register allocator prefers an order such that callee-saved-registers are allocated after non-callee-saved-registers to avoid having to spill the CSR. This sorting characteristic occurs only as a tie breaker to the Weight calculation. This is a good idea since the weight calculation is pretty complex and I'm sure it is a pretty stable metric. I think its pretty reasonable to agree that whether a register is callee-saved or not is a better tie breaker than register ID. I think this is evident by the test diff, since the changes all seem to have no impact or improve the register allocation.
353 lines
12 KiB
C++
353 lines
12 KiB
C++
//===- CalcSpillWeights.cpp -----------------------------------------------===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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#include "llvm/CodeGen/CalcSpillWeights.h"
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#include "llvm/ADT/SmallPtrSet.h"
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#include "llvm/CodeGen/LiveInterval.h"
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#include "llvm/CodeGen/LiveIntervals.h"
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#include "llvm/CodeGen/MachineFunction.h"
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#include "llvm/CodeGen/MachineInstr.h"
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#include "llvm/CodeGen/MachineLoopInfo.h"
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#include "llvm/CodeGen/MachineOperand.h"
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#include "llvm/CodeGen/MachineRegisterInfo.h"
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#include "llvm/CodeGen/StackMaps.h"
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#include "llvm/CodeGen/TargetInstrInfo.h"
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#include "llvm/CodeGen/TargetRegisterInfo.h"
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#include "llvm/CodeGen/TargetSubtargetInfo.h"
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#include "llvm/CodeGen/VirtRegMap.h"
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#include "llvm/Support/Debug.h"
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#include "llvm/Support/MathExtras.h"
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#include "llvm/Support/raw_ostream.h"
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#include <cassert>
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#include <tuple>
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using namespace llvm;
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#define DEBUG_TYPE "calcspillweights"
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void VirtRegAuxInfo::calculateSpillWeightsAndHints() {
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LLVM_DEBUG(dbgs() << "********** Compute Spill Weights **********\n"
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<< "********** Function: " << MF.getName() << '\n');
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MachineRegisterInfo &MRI = MF.getRegInfo();
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for (unsigned I = 0, E = MRI.getNumVirtRegs(); I != E; ++I) {
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Register Reg = Register::index2VirtReg(I);
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if (MRI.reg_nodbg_empty(Reg))
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continue;
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calculateSpillWeightAndHint(LIS.getInterval(Reg));
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}
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}
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// Return the preferred allocation register for reg, given a COPY instruction.
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Register VirtRegAuxInfo::copyHint(const MachineInstr *MI, Register Reg,
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const TargetRegisterInfo &TRI,
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const MachineRegisterInfo &MRI) {
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unsigned Sub, HSub;
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Register HReg;
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if (MI->getOperand(0).getReg() == Reg) {
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Sub = MI->getOperand(0).getSubReg();
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HReg = MI->getOperand(1).getReg();
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HSub = MI->getOperand(1).getSubReg();
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} else {
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Sub = MI->getOperand(1).getSubReg();
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HReg = MI->getOperand(0).getReg();
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HSub = MI->getOperand(0).getSubReg();
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}
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if (!HReg)
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return 0;
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if (HReg.isVirtual())
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return Sub == HSub ? HReg : Register();
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const TargetRegisterClass *RC = MRI.getRegClass(Reg);
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MCRegister CopiedPReg = HSub ? TRI.getSubReg(HReg, HSub) : HReg.asMCReg();
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if (RC->contains(CopiedPReg))
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return CopiedPReg;
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// Check if reg:sub matches so that a super register could be hinted.
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if (Sub)
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return TRI.getMatchingSuperReg(CopiedPReg, Sub, RC);
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return Register();
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}
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// Check if all values in LI are rematerializable
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bool VirtRegAuxInfo::isRematerializable(const LiveInterval &LI,
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const LiveIntervals &LIS,
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const VirtRegMap &VRM,
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const TargetInstrInfo &TII) {
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Register Reg = LI.reg();
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Register Original = VRM.getOriginal(Reg);
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for (LiveInterval::const_vni_iterator I = LI.vni_begin(), E = LI.vni_end();
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I != E; ++I) {
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const VNInfo *VNI = *I;
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if (VNI->isUnused())
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continue;
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if (VNI->isPHIDef())
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return false;
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MachineInstr *MI = LIS.getInstructionFromIndex(VNI->def);
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assert(MI && "Dead valno in interval");
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// Trace copies introduced by live range splitting. The inline
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// spiller can rematerialize through these copies, so the spill
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// weight must reflect this.
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while (TII.isFullCopyInstr(*MI)) {
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// The copy destination must match the interval register.
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if (MI->getOperand(0).getReg() != Reg)
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return false;
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// Get the source register.
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Reg = MI->getOperand(1).getReg();
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// If the original (pre-splitting) registers match this
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// copy came from a split.
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if (!Reg.isVirtual() || VRM.getOriginal(Reg) != Original)
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return false;
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// Follow the copy live-in value.
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const LiveInterval &SrcLI = LIS.getInterval(Reg);
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LiveQueryResult SrcQ = SrcLI.Query(VNI->def);
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VNI = SrcQ.valueIn();
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assert(VNI && "Copy from non-existing value");
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if (VNI->isPHIDef())
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return false;
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MI = LIS.getInstructionFromIndex(VNI->def);
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assert(MI && "Dead valno in interval");
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}
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if (!TII.isTriviallyReMaterializable(*MI))
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return false;
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}
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return true;
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}
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bool VirtRegAuxInfo::isLiveAtStatepointVarArg(LiveInterval &LI) {
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return any_of(VRM.getRegInfo().reg_operands(LI.reg()),
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[](MachineOperand &MO) {
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MachineInstr *MI = MO.getParent();
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if (MI->getOpcode() != TargetOpcode::STATEPOINT)
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return false;
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return StatepointOpers(MI).getVarIdx() <= MO.getOperandNo();
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});
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}
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void VirtRegAuxInfo::calculateSpillWeightAndHint(LiveInterval &LI) {
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float Weight = weightCalcHelper(LI);
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// Check if unspillable.
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if (Weight < 0)
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return;
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LI.setWeight(Weight);
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}
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static bool canMemFoldInlineAsm(LiveInterval &LI,
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const MachineRegisterInfo &MRI) {
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for (const MachineOperand &MO : MRI.reg_operands(LI.reg())) {
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const MachineInstr *MI = MO.getParent();
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if (MI->isInlineAsm() && MI->mayFoldInlineAsmRegOp(MI->getOperandNo(&MO)))
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return true;
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}
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return false;
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}
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float VirtRegAuxInfo::weightCalcHelper(LiveInterval &LI, SlotIndex *Start,
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SlotIndex *End) {
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MachineRegisterInfo &MRI = MF.getRegInfo();
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const TargetRegisterInfo &TRI = *MF.getSubtarget().getRegisterInfo();
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const TargetInstrInfo &TII = *MF.getSubtarget().getInstrInfo();
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MachineBasicBlock *MBB = nullptr;
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float TotalWeight = 0;
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unsigned NumInstr = 0; // Number of instructions using LI
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SmallPtrSet<MachineInstr *, 8> Visited;
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std::pair<unsigned, Register> TargetHint = MRI.getRegAllocationHint(LI.reg());
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if (LI.isSpillable()) {
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Register Reg = LI.reg();
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Register Original = VRM.getOriginal(Reg);
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const LiveInterval &OrigInt = LIS.getInterval(Original);
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// li comes from a split of OrigInt. If OrigInt was marked
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// as not spillable, make sure the new interval is marked
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// as not spillable as well.
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if (!OrigInt.isSpillable())
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LI.markNotSpillable();
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}
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// Don't recompute spill weight for an unspillable register.
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bool IsSpillable = LI.isSpillable();
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bool IsLocalSplitArtifact = Start && End;
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// Do not update future local split artifacts.
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bool ShouldUpdateLI = !IsLocalSplitArtifact;
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if (IsLocalSplitArtifact) {
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MachineBasicBlock *LocalMBB = LIS.getMBBFromIndex(*End);
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assert(LocalMBB == LIS.getMBBFromIndex(*Start) &&
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"start and end are expected to be in the same basic block");
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// Local split artifact will have 2 additional copy instructions and they
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// will be in the same BB.
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// localLI = COPY other
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// ...
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// other = COPY localLI
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TotalWeight +=
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LiveIntervals::getSpillWeight(true, false, &MBFI, LocalMBB, PSI);
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TotalWeight +=
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LiveIntervals::getSpillWeight(false, true, &MBFI, LocalMBB, PSI);
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NumInstr += 2;
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}
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// CopyHint is a sortable hint derived from a COPY instruction.
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struct CopyHint {
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Register Reg;
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float Weight;
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bool IsCSR;
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CopyHint(Register R, float W, bool IsCSR)
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: Reg(R), Weight(W), IsCSR(IsCSR) {}
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bool operator<(const CopyHint &Rhs) const {
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// Always prefer any physreg hint.
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if (Reg.isPhysical() != Rhs.Reg.isPhysical())
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return Reg.isPhysical();
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if (Weight != Rhs.Weight)
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return (Weight > Rhs.Weight);
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// Prefer non-CSR to CSR.
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if (Reg.isPhysical() && IsCSR != Rhs.IsCSR)
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return !IsCSR;
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return Reg.id() < Rhs.Reg.id(); // Tie-breaker.
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}
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};
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bool IsExiting = false;
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SmallDenseMap<Register, float, 8> Hint;
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for (MachineRegisterInfo::reg_instr_nodbg_iterator
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I = MRI.reg_instr_nodbg_begin(LI.reg()),
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E = MRI.reg_instr_nodbg_end();
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I != E;) {
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MachineInstr *MI = &*(I++);
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// For local split artifacts, we are interested only in instructions between
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// the expected start and end of the range.
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SlotIndex SI = LIS.getInstructionIndex(*MI);
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if (IsLocalSplitArtifact && ((SI < *Start) || (SI > *End)))
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continue;
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NumInstr++;
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bool identityCopy = false;
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auto DestSrc = TII.isCopyInstr(*MI);
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if (DestSrc) {
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const MachineOperand *DestRegOp = DestSrc->Destination;
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const MachineOperand *SrcRegOp = DestSrc->Source;
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identityCopy = DestRegOp->getReg() == SrcRegOp->getReg() &&
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DestRegOp->getSubReg() == SrcRegOp->getSubReg();
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}
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if (identityCopy || MI->isImplicitDef())
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continue;
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if (!Visited.insert(MI).second)
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continue;
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// For terminators that produce values, ask the backend if the register is
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// not spillable.
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if (TII.isUnspillableTerminator(MI) &&
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MI->definesRegister(LI.reg(), /*TRI=*/nullptr)) {
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LI.markNotSpillable();
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return -1.0f;
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}
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// Force Weight onto the stack so that x86 doesn't add hidden precision.
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stack_float_t Weight = 1.0f;
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if (IsSpillable) {
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// Get loop info for mi.
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if (MI->getParent() != MBB) {
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MBB = MI->getParent();
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const MachineLoop *Loop = Loops.getLoopFor(MBB);
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IsExiting = Loop ? Loop->isLoopExiting(MBB) : false;
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}
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// Calculate instr weight.
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bool Reads, Writes;
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std::tie(Reads, Writes) = MI->readsWritesVirtualRegister(LI.reg());
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Weight = LiveIntervals::getSpillWeight(Writes, Reads, &MBFI, *MI, PSI);
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// Give extra weight to what looks like a loop induction variable update.
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if (Writes && IsExiting && LIS.isLiveOutOfMBB(LI, MBB))
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Weight *= 3;
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TotalWeight += Weight;
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}
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// Get allocation hints from copies.
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if (!TII.isCopyInstr(*MI))
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continue;
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Register HintReg = copyHint(MI, LI.reg(), TRI, MRI);
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if (HintReg && (HintReg.isVirtual() || MRI.isAllocatable(HintReg)))
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Hint[HintReg] += Weight;
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}
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// Pass all the sorted copy hints to mri.
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if (ShouldUpdateLI && Hint.size()) {
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// Remove a generic hint if previously added by target.
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if (TargetHint.first == 0 && TargetHint.second)
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MRI.clearSimpleHint(LI.reg());
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// Don't add the target-type hint again.
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Register SkipReg = TargetHint.first != 0 ? TargetHint.second : Register();
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SmallVector<CopyHint, 8> RegHints;
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for (const auto &[Reg, Weight] : Hint) {
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if (Reg != SkipReg)
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RegHints.emplace_back(
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Reg, Weight,
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Reg.isPhysical() ? TRI.isCalleeSavedPhysReg(Reg, MF) : false);
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}
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sort(RegHints);
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for (const auto &[Reg, _, __] : RegHints)
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MRI.addRegAllocationHint(LI.reg(), Reg);
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// Weakly boost the spill weight of hinted registers.
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TotalWeight *= 1.01F;
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}
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// If the live interval was already unspillable, leave it that way.
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if (!IsSpillable)
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return -1.0;
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// Mark li as unspillable if all live ranges are tiny and the interval
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// is not live at any reg mask. If the interval is live at a reg mask
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// spilling may be required. If li is live as use in statepoint instruction
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// spilling may be required due to if we mark interval with use in statepoint
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// as not spillable we are risky to end up with no register to allocate.
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// At the same time STATEPOINT instruction is perfectly fine to have this
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// operand on stack, so spilling such interval and folding its load from stack
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// into instruction itself makes perfect sense.
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if (ShouldUpdateLI && LI.isZeroLength(LIS.getSlotIndexes()) &&
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!LI.isLiveAtIndexes(LIS.getRegMaskSlots()) &&
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!isLiveAtStatepointVarArg(LI) && !canMemFoldInlineAsm(LI, MRI)) {
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LI.markNotSpillable();
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return -1.0;
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}
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// If all of the definitions of the interval are re-materializable,
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// it is a preferred candidate for spilling.
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// FIXME: this gets much more complicated once we support non-trivial
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// re-materialization.
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if (isRematerializable(LI, LIS, VRM, *MF.getSubtarget().getInstrInfo()))
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TotalWeight *= 0.5F;
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// Finally, we scale the weight by the scale factor of register class.
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const TargetRegisterClass *RC = MRI.getRegClass(LI.reg());
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TotalWeight *= TRI.getSpillWeightScaleFactor(RC);
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if (IsLocalSplitArtifact)
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return normalize(TotalWeight, Start->distance(*End), NumInstr);
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return normalize(TotalWeight, LI.getSize(), NumInstr);
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}
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