3041fa6c7a
DenseSet, SmallPtrSet, SmallSet, SetVector, and StringSet recently gained C++23-style insert_range. This patch replaces: Dest.insert(Src.begin(), Src.end()); with: Dest.insert_range(Src); This patch does not touch custom begin like succ_begin for now.
948 lines
38 KiB
C++
948 lines
38 KiB
C++
//===- GPUTransformOps.cpp - Implementation of GPU transform ops ----------===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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#include "mlir/Dialect/GPU/TransformOps/GPUTransformOps.h"
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#include "mlir/Conversion/GPUCommon/GPUCommonPass.h"
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#include "mlir/Conversion/GPUToNVVM/GPUToNVVMPass.h"
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#include "mlir/Conversion/LLVMCommon/TypeConverter.h"
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#include "mlir/Dialect/Affine/IR/AffineOps.h"
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#include "mlir/Dialect/Arith/IR/Arith.h"
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#include "mlir/Dialect/Func/IR/FuncOps.h"
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#include "mlir/Dialect/GPU/IR/GPUDialect.h"
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#include "mlir/Dialect/GPU/TransformOps/Utils.h"
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#include "mlir/Dialect/GPU/Transforms/Passes.h"
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#include "mlir/Dialect/LLVMIR/NVVMDialect.h"
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#include "mlir/Dialect/MemRef/IR/MemRef.h"
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#include "mlir/Dialect/SCF/IR/DeviceMappingInterface.h"
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#include "mlir/Dialect/SCF/IR/SCF.h"
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#include "mlir/Dialect/Transform/IR/TransformDialect.h"
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#include "mlir/Dialect/Transform/Interfaces/TransformInterfaces.h"
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#include "mlir/Dialect/Utils/IndexingUtils.h"
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#include "mlir/Dialect/Vector/IR/VectorOps.h"
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#include "mlir/Dialect/Vector/Transforms/VectorTransforms.h"
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#include "mlir/IR/AffineExpr.h"
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#include "mlir/IR/Builders.h"
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#include "mlir/IR/BuiltinAttributes.h"
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#include "mlir/IR/IRMapping.h"
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#include "mlir/IR/MLIRContext.h"
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#include "mlir/IR/OpDefinition.h"
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#include "mlir/IR/Visitors.h"
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#include "mlir/Support/LLVM.h"
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#include "mlir/Transforms/DialectConversion.h"
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#include "llvm/ADT/STLExtras.h"
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#include "llvm/ADT/SmallVector.h"
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#include "llvm/ADT/TypeSwitch.h"
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#include "llvm/Support/Debug.h"
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#include "llvm/Support/ErrorHandling.h"
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#include <type_traits>
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using namespace mlir;
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using namespace mlir::gpu;
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using namespace mlir::transform;
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using namespace mlir::transform::gpu;
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#define DEBUG_TYPE "gpu-transforms"
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#define DEBUG_TYPE_ALIAS "gpu-transforms-alias"
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#define DBGS() (llvm::dbgs() << '[' << DEBUG_TYPE << "] ")
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#define LDBG(X) LLVM_DEBUG(DBGS() << X << "\n")
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#define DBGS_ALIAS() (llvm::dbgs() << '[' << DEBUG_TYPE_ALIAS << "] ")
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//===----------------------------------------------------------------------===//
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// Apply...ConversionPatternsOp
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//===----------------------------------------------------------------------===//
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void transform::ApplyGPUToNVVMConversionPatternsOp::populatePatterns(
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TypeConverter &typeConverter, RewritePatternSet &patterns) {
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auto &llvmTypeConverter = static_cast<LLVMTypeConverter &>(typeConverter);
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// NVVM uses alloca in the default address space to represent private
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// memory allocations, so drop private annotations. NVVM uses address
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// space 3 for shared memory. NVVM uses the default address space to
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// represent global memory.
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// Used in populateGpuToNVVMConversionPatternsso attaching here for now.
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// TODO: We should have a single to_nvvm_type_converter.
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populateGpuMemorySpaceAttributeConversions(
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llvmTypeConverter, [](AddressSpace space) -> unsigned {
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switch (space) {
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case AddressSpace::Global:
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return static_cast<unsigned>(
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NVVM::NVVMMemorySpace::kGlobalMemorySpace);
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case AddressSpace::Workgroup:
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return static_cast<unsigned>(
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NVVM::NVVMMemorySpace::kSharedMemorySpace);
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case AddressSpace::Private:
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return 0;
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}
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llvm_unreachable("unknown address space enum value");
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return 0;
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});
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// Used in GPUToNVVM/WmmaOpsToNvvm.cpp so attaching here for now.
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// TODO: We should have a single to_nvvm_type_converter.
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llvmTypeConverter.addConversion(
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[&](MMAMatrixType type) -> Type { return convertMMAToLLVMType(type); });
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// Set higher benefit, so patterns will run before generic LLVM lowering.
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populateGpuToNVVMConversionPatterns(llvmTypeConverter, patterns,
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getBenefit());
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}
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LogicalResult
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transform::ApplyGPUToNVVMConversionPatternsOp::verifyTypeConverter(
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transform::TypeConverterBuilderOpInterface builder) {
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if (builder.getTypeConverterType() != "LLVMTypeConverter")
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return emitOpError("expected LLVMTypeConverter");
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return success();
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}
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void transform::ApplyGPUWwmaToNVVMConversionPatternsOp::populatePatterns(
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TypeConverter &typeConverter, RewritePatternSet &patterns) {
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auto &llvmTypeConverter = static_cast<LLVMTypeConverter &>(typeConverter);
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populateGpuWMMAToNVVMConversionPatterns(llvmTypeConverter, patterns);
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}
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LogicalResult
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transform::ApplyGPUWwmaToNVVMConversionPatternsOp::verifyTypeConverter(
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transform::TypeConverterBuilderOpInterface builder) {
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if (builder.getTypeConverterType() != "LLVMTypeConverter")
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return emitOpError("expected LLVMTypeConverter");
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return success();
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}
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void transform::ApplyGPUSubgroupReduceToNVVMConversionPatternsOp::
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populatePatterns(TypeConverter &typeConverter,
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RewritePatternSet &patterns) {
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auto &llvmTypeConverter = static_cast<LLVMTypeConverter &>(typeConverter);
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populateGpuSubgroupReduceOpLoweringPattern(llvmTypeConverter, patterns);
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}
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LogicalResult transform::ApplyGPUSubgroupReduceToNVVMConversionPatternsOp::
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verifyTypeConverter(transform::TypeConverterBuilderOpInterface builder) {
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if (builder.getTypeConverterType() != "LLVMTypeConverter")
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return emitOpError("expected LLVMTypeConverter");
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return success();
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}
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//===----------------------------------------------------------------------===//
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// Apply...PatternsOp
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//===----------------------------------------------------------------------===//s
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void ApplyGPURewritePatternsOp::populatePatterns(RewritePatternSet &patterns) {
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populateGpuRewritePatterns(patterns);
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}
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//===----------------------------------------------------------------------===//
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// ApplyUnrollVectorsSubgroupMmaOp
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//===----------------------------------------------------------------------===//
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/// Pick an unrolling order that will allow tensorcore operation to reuse LHS
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/// register.
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static std::optional<SmallVector<int64_t>>
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gpuMmaUnrollOrder(vector::ContractionOp contract) {
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SmallVector<int64_t> order;
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// First make reduction the outer dimensions.
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for (auto [index, iter] : llvm::enumerate(contract.getIteratorTypes())) {
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if (vector::isReductionIterator(iter)) {
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order.push_back(index);
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}
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}
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llvm::SmallDenseSet<int64_t> dims;
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for (AffineExpr expr : contract.getIndexingMapsArray()[0].getResults()) {
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dims.insert(cast<AffineDimExpr>(expr).getPosition());
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}
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// Then parallel dimensions that are part of Lhs as we want to re-use Lhs.
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for (auto [index, iter] : llvm::enumerate(contract.getIteratorTypes())) {
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if (vector::isParallelIterator(iter) && dims.count(index)) {
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order.push_back(index);
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}
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}
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// Then the remaining parallel loops.
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for (auto [index, iter] : llvm::enumerate(contract.getIteratorTypes())) {
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if (vector::isParallelIterator(iter) && !dims.count(index)) {
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order.push_back(index);
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}
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}
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return order;
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}
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/// Returns the target vector size for the target operation based on the native
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/// vector size specified with `m`, `n`, and `k`.
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static std::optional<SmallVector<int64_t>>
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getSubgroupMmaNativeVectorSize(Operation *op, int64_t m, int64_t n, int64_t k) {
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if (auto contract = dyn_cast<vector::ContractionOp>(op)) {
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int64_t contractRank = contract.getIteratorTypes().size();
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if (contractRank < 3)
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return std::nullopt;
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SmallVector<int64_t> nativeSize(contractRank - 3, 1);
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nativeSize.append({m, n, k});
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return nativeSize;
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}
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if (auto writeOp = dyn_cast<vector::TransferWriteOp>(op)) {
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int64_t writeRank = writeOp.getVectorType().getRank();
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if (writeRank < 2)
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return std::nullopt;
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SmallVector<int64_t> nativeSize(writeRank - 2, 1);
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nativeSize.append({m, n});
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return nativeSize;
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}
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if (auto readOp = dyn_cast<vector::TransferReadOp>(op)) {
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// Transfer read ops may need different shapes based on how they are being
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// used. For simplicity just match the shape used by the extract strided op.
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VectorType sliceType;
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for (Operation *users : op->getUsers()) {
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auto extract = dyn_cast<vector::ExtractStridedSliceOp>(users);
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if (!extract)
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return std::nullopt;
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auto vecType = cast<VectorType>(extract.getResult().getType());
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if (sliceType && sliceType != vecType)
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return std::nullopt;
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sliceType = vecType;
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}
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return llvm::to_vector(sliceType.getShape());
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}
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if ((OpTrait::hasElementwiseMappableTraits(op) && op->getNumResults() == 1)) {
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if (auto vecType = dyn_cast<VectorType>(op->getResultTypes()[0])) {
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// TODO: The condition for unrolling elementwise should be restricted
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// only to operations that need unrolling (connected to the contract).
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if (vecType.getRank() < 2)
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return std::nullopt;
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// First check whether there is a slice to infer the shape from. This is
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// required for cases where the accumulator type differs from the input
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// types, in which case we will see an `arith.ext_` between the contract
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// and transfer_read which needs to be unrolled.
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VectorType sliceType;
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for (Operation *users : op->getUsers()) {
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auto extract = dyn_cast<vector::ExtractStridedSliceOp>(users);
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if (!extract)
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return std::nullopt;
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auto vecType = cast<VectorType>(extract.getResult().getType());
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if (sliceType && sliceType != vecType)
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return std::nullopt;
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sliceType = vecType;
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}
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if (sliceType)
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return llvm::to_vector(sliceType.getShape());
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// Else unroll for trailing elementwise.
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SmallVector<int64_t> nativeSize(vecType.getRank() - 2, 1);
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// Map elementwise ops to the output shape.
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nativeSize.append({m, n});
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return nativeSize;
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}
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}
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return std::nullopt;
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}
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void transform::ApplyUnrollVectorsSubgroupMmaOp::populatePatterns(
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RewritePatternSet &patterns) {
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auto unrollOrder = [](Operation *op) -> std::optional<SmallVector<int64_t>> {
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auto contract = dyn_cast<vector::ContractionOp>(op);
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if (!contract)
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return std::nullopt;
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return gpuMmaUnrollOrder(contract);
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};
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int64_t m = getM();
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int64_t n = getN();
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int64_t k = getK();
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auto nativeShapeFn =
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[m, n, k](Operation *op) -> std::optional<SmallVector<int64_t>> {
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return getSubgroupMmaNativeVectorSize(op, m, n, k);
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};
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vector::populateVectorUnrollPatterns(
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patterns, vector::UnrollVectorOptions()
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.setNativeShapeFn(nativeShapeFn)
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.setUnrollTraversalOrderFn(unrollOrder));
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}
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//===----------------------------------------------------------------------===//
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// EliminateBarriersOp
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//===----------------------------------------------------------------------===//
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void EliminateBarriersOp::populatePatterns(RewritePatternSet &patterns) {
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populateGpuEliminateBarriersPatterns(patterns);
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}
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//===----------------------------------------------------------------------===//
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// Block and thread mapping utilities.
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//===----------------------------------------------------------------------===//
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namespace {
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/// Local types used for mapping verification.
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struct MappingKind {};
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struct BlockMappingKind : MappingKind {};
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struct ThreadMappingKind : MappingKind {};
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} // namespace
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static DiagnosedSilenceableFailure
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definiteFailureHelper(std::optional<TransformOpInterface> transformOp,
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Operation *target, const Twine &message) {
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if (transformOp.has_value())
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return transformOp->emitDefiniteFailure() << message;
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return emitDefiniteFailure(target, message);
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}
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/// Check if given mapping attributes are one of the desired attributes
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template <typename MappingKindType>
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static DiagnosedSilenceableFailure
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checkMappingAttributeTypes(std::optional<TransformOpInterface> transformOp,
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scf::ForallOp forallOp) {
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if (!forallOp.getMapping().has_value()) {
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return definiteFailureHelper(transformOp, forallOp,
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"scf.forall op requires a mapping attribute");
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}
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bool hasBlockMapping = llvm::any_of(forallOp.getMapping().value(),
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llvm::IsaPred<GPUBlockMappingAttr>);
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bool hasWarpgroupMapping = llvm::any_of(
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forallOp.getMapping().value(), llvm::IsaPred<GPUWarpgroupMappingAttr>);
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bool hasWarpMapping = llvm::any_of(forallOp.getMapping().value(),
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llvm::IsaPred<GPUWarpMappingAttr>);
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bool hasThreadMapping = llvm::any_of(forallOp.getMapping().value(),
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llvm::IsaPred<GPUThreadMappingAttr>);
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int64_t countMappingTypes = 0;
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countMappingTypes += hasBlockMapping ? 1 : 0;
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countMappingTypes += hasWarpgroupMapping ? 1 : 0;
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countMappingTypes += hasWarpMapping ? 1 : 0;
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countMappingTypes += hasThreadMapping ? 1 : 0;
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if (countMappingTypes > 1) {
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return definiteFailureHelper(
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transformOp, forallOp,
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"cannot mix different mapping types, use nesting");
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}
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if (std::is_same<MappingKindType, BlockMappingKind>::value &&
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!hasBlockMapping) {
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return definiteFailureHelper(
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transformOp, forallOp,
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"scf.forall op requires a mapping attribute of kind 'block'");
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}
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if (std::is_same<MappingKindType, ThreadMappingKind>::value &&
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!hasThreadMapping && !hasWarpMapping && !hasWarpgroupMapping) {
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return definiteFailureHelper(transformOp, forallOp,
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"scf.forall op requires a mapping attribute "
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"of kind 'thread' or 'warp'");
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}
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DenseSet<Attribute> seen;
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for (Attribute map : forallOp.getMapping()->getValue()) {
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if (seen.contains(map)) {
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return definiteFailureHelper(
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transformOp, forallOp,
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"duplicate attribute, cannot map different loops "
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"to the same mapping id");
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}
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seen.insert(map);
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}
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auto isLinear = [](Attribute a) {
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return cast<DeviceMappingAttrInterface>(a).isLinearMapping();
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};
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if (llvm::any_of(forallOp.getMapping()->getValue(), isLinear) &&
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!llvm::all_of(forallOp.getMapping()->getValue(), isLinear)) {
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return definiteFailureHelper(
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transformOp, forallOp,
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"cannot mix linear and non-linear mapping modes");
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}
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return DiagnosedSilenceableFailure::success();
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}
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template <typename MappingKindType>
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static DiagnosedSilenceableFailure
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verifyGpuMapping(std::optional<TransformOpInterface> transformOp,
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scf::ForallOp forallOp) {
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// Check the types of the mapping attributes match.
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DiagnosedSilenceableFailure typeRes =
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checkMappingAttributeTypes<MappingKindType>(transformOp, forallOp);
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if (!typeRes.succeeded())
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return typeRes;
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// Perform other non-types verifications.
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if (!forallOp.isNormalized())
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return definiteFailureHelper(transformOp, forallOp,
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"unsupported non-normalized loops");
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if (forallOp.getNumResults() > 0)
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return definiteFailureHelper(transformOp, forallOp,
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"only bufferized scf.forall can be mapped");
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bool useLinearMapping = cast<DeviceMappingAttrInterface>(
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forallOp.getMapping()->getValue().front())
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.isLinearMapping();
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// TODO: This would be more natural with support for Optional<EnumParameter>
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// in GPUDeviceMappingAttr.
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int64_t maxNumMappingsSupported =
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useLinearMapping ? (getMaxEnumValForMappingId() -
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static_cast<uint64_t>(MappingId::DimZ))
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: 3;
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if (forallOp.getRank() > maxNumMappingsSupported) {
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return definiteFailureHelper(transformOp, forallOp,
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"scf.forall with rank > ")
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<< maxNumMappingsSupported
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<< " does not lower for the specified mapping attribute type";
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}
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auto numParallelIterations =
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getConstantIntValues(forallOp.getMixedUpperBound());
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if (!forallOp.isNormalized() || !numParallelIterations.has_value()) {
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return definiteFailureHelper(
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transformOp, forallOp,
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"requires statically sized, normalized forall op");
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}
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return DiagnosedSilenceableFailure::success();
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}
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/// Struct to return the result of the rewrite of a forall operation.
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struct ForallRewriteResult {
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SmallVector<int64_t> mappingSizes;
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SmallVector<Value> mappingIds;
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};
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/// Helper to replace ids of dimensions known to be 1 by 0 to simplify the IR.
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template <typename OpTy, typename OperationOrBlock>
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static void
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replaceUnitMappingIdsHelper(RewriterBase &rewriter, Location loc,
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OperationOrBlock *parent, Value replacement,
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ArrayRef<int64_t> availableMappingSizes) {
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parent->walk([&](OpTy idOp) {
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if (availableMappingSizes[static_cast<int64_t>(idOp.getDimension())] == 1)
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rewriter.replaceAllUsesWith(idOp.getResult(), replacement);
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});
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}
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static DiagnosedSilenceableFailure rewriteOneForallCommonImpl(
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RewriterBase &rewriter, std::optional<TransformOpInterface> transformOp,
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scf::ForallOp forallOp, ArrayRef<int64_t> availableMappingSizes,
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ForallRewriteResult &result, const GpuIdBuilder &gpuIdBuilder) {
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LDBG("--start rewriteOneForallCommonImpl");
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// Step 1. Complete the mapping to a full mapping (with 1s) if necessary.
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auto numParallelIterations =
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getConstantIntValues(forallOp.getMixedUpperBound());
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assert(forallOp.isNormalized() && numParallelIterations.has_value() &&
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"requires statically sized, normalized forall op");
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SmallVector<int64_t> tmpMappingSizes = numParallelIterations.value();
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SetVector<Attribute> forallMappingAttrs;
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forallMappingAttrs.insert_range(forallOp.getMapping()->getValue());
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auto comparator = [](Attribute a, Attribute b) -> bool {
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return cast<DeviceMappingAttrInterface>(a).getMappingId() <
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cast<DeviceMappingAttrInterface>(b).getMappingId();
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};
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// Step 1.b. In the linear case, compute the max mapping to avoid needlessly
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// mapping all dimensions. In the 3-D mapping case we need to map all
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// dimensions.
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DeviceMappingAttrInterface maxMapping = cast<DeviceMappingAttrInterface>(
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*llvm::max_element(forallMappingAttrs, comparator));
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DeviceMappingAttrInterface maxLinearMapping;
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if (maxMapping.isLinearMapping())
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maxLinearMapping = maxMapping;
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for (auto attr : gpuIdBuilder.mappingAttributes) {
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// If attr overflows, just skip.
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if (maxLinearMapping && comparator(maxLinearMapping, attr))
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continue;
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// Try to insert. If element was already present, just continue.
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if (!forallMappingAttrs.insert(attr))
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continue;
|
|
// Otherwise, we have a new insertion without a size -> use size 1.
|
|
tmpMappingSizes.push_back(1);
|
|
}
|
|
LLVM_DEBUG(
|
|
llvm::interleaveComma(
|
|
tmpMappingSizes,
|
|
DBGS() << "----tmpMappingSizes extracted from scf.forall op: ");
|
|
llvm::dbgs() << "\n");
|
|
|
|
// Step 2. sort the values by the corresponding DeviceMappingAttrInterface.
|
|
SmallVector<int64_t> forallMappingSizes = getValuesSortedByKey(
|
|
forallMappingAttrs.getArrayRef(), tmpMappingSizes, comparator);
|
|
LLVM_DEBUG(llvm::interleaveComma(forallMappingSizes,
|
|
DBGS() << "----forallMappingSizes: ");
|
|
llvm::dbgs() << "\n"; llvm::interleaveComma(
|
|
forallMappingAttrs, DBGS() << "----forallMappingAttrs: ");
|
|
llvm::dbgs() << "\n");
|
|
|
|
// Step 3. Generate the mappingIdOps using the provided generator.
|
|
Location loc = forallOp.getLoc();
|
|
OpBuilder::InsertionGuard guard(rewriter);
|
|
rewriter.setInsertionPoint(forallOp);
|
|
SmallVector<int64_t> originalBasis(availableMappingSizes);
|
|
bool originalBasisWasProvided = !originalBasis.empty();
|
|
if (!originalBasisWasProvided) {
|
|
originalBasis = forallMappingSizes;
|
|
while (originalBasis.size() < 3)
|
|
originalBasis.push_back(1);
|
|
}
|
|
|
|
IdBuilderResult builderResult =
|
|
gpuIdBuilder.idBuilder(rewriter, loc, forallMappingSizes, originalBasis);
|
|
|
|
// Step 4. Map the induction variables to the mappingIdOps, this may involve
|
|
// a permutation.
|
|
SmallVector<Value> mappingIdOps = builderResult.mappingIdOps;
|
|
IRMapping bvm;
|
|
for (auto [iv, dim] : llvm::zip_equal(
|
|
forallOp.getInductionVars(),
|
|
forallMappingAttrs.getArrayRef().take_front(forallOp.getRank()))) {
|
|
auto mappingAttr = cast<DeviceMappingAttrInterface>(dim);
|
|
Value peIdOp = mappingIdOps[mappingAttr.getRelativeIndex()];
|
|
bvm.map(iv, peIdOp);
|
|
}
|
|
|
|
// Step 5. If the originalBasis is already known, create conditionals to
|
|
// predicate the region. Otherwise, the current forall determines the
|
|
// originalBasis and no predication occurs.
|
|
Value predicate;
|
|
if (originalBasisWasProvided) {
|
|
SmallVector<int64_t> activeMappingSizes = builderResult.activeMappingSizes;
|
|
SmallVector<int64_t> availableMappingSizes =
|
|
builderResult.availableMappingSizes;
|
|
SmallVector<Value> activeIdOps = builderResult.activeIdOps;
|
|
// clang-format off
|
|
LLVM_DEBUG(
|
|
llvm::interleaveComma(
|
|
activeMappingSizes, DBGS() << "----activeMappingSizes: ");
|
|
llvm::dbgs() << "\n";
|
|
llvm::interleaveComma(
|
|
availableMappingSizes, DBGS() << "----availableMappingSizes: ");
|
|
llvm::dbgs() << "\n";
|
|
llvm::interleaveComma(activeIdOps, DBGS() << "----activeIdOps: ");
|
|
llvm::dbgs() << "\n");
|
|
// clang-format on
|
|
for (auto [activeId, activeMappingSize, availableMappingSize] :
|
|
llvm::zip_equal(activeIdOps, activeMappingSizes,
|
|
availableMappingSizes)) {
|
|
if (activeMappingSize > availableMappingSize) {
|
|
return definiteFailureHelper(
|
|
transformOp, forallOp,
|
|
"Trying to map to fewer GPU threads than loop iterations but "
|
|
"overprovisioning is not yet supported. "
|
|
"Try additional tiling of the before mapping or map to more "
|
|
"threads.");
|
|
}
|
|
if (activeMappingSize == availableMappingSize)
|
|
continue;
|
|
Value idx =
|
|
rewriter.create<arith::ConstantIndexOp>(loc, activeMappingSize);
|
|
Value tmpPredicate = rewriter.create<arith::CmpIOp>(
|
|
loc, arith::CmpIPredicate::ult, activeId, idx);
|
|
LDBG("----predicate: " << tmpPredicate);
|
|
predicate = predicate ? rewriter.create<arith::AndIOp>(loc, predicate,
|
|
tmpPredicate)
|
|
: tmpPredicate;
|
|
}
|
|
}
|
|
|
|
// Step 6. Move the body of forallOp.
|
|
// Erase the terminator first, it will not be used.
|
|
rewriter.eraseOp(forallOp.getTerminator());
|
|
Block *targetBlock;
|
|
Block::iterator insertionPoint;
|
|
if (predicate) {
|
|
// Step 6.a. If predicated, move at the beginning.
|
|
auto ifOp = rewriter.create<scf::IfOp>(loc, predicate,
|
|
/*withElseRegion=*/false);
|
|
targetBlock = ifOp.thenBlock();
|
|
insertionPoint = ifOp.thenBlock()->begin();
|
|
} else {
|
|
// Step 6.b. Otherwise, move inline just at the rewriter insertion
|
|
// point.
|
|
targetBlock = forallOp->getBlock();
|
|
insertionPoint = rewriter.getInsertionPoint();
|
|
}
|
|
Block &sourceBlock = forallOp.getRegion().front();
|
|
targetBlock->getOperations().splice(insertionPoint,
|
|
sourceBlock.getOperations());
|
|
|
|
// Step 7. RAUW indices.
|
|
for (Value loopIndex : forallOp.getInductionVars()) {
|
|
Value threadIdx = bvm.lookup(loopIndex);
|
|
rewriter.replaceAllUsesWith(loopIndex, threadIdx);
|
|
}
|
|
|
|
// Step 8. Erase old op.
|
|
rewriter.eraseOp(forallOp);
|
|
|
|
LLVM_DEBUG(llvm::interleaveComma(forallMappingSizes,
|
|
DBGS() << "----result forallMappingSizes: ");
|
|
llvm::dbgs() << "\n"; llvm::interleaveComma(
|
|
mappingIdOps, DBGS() << "----result mappingIdOps: ");
|
|
llvm::dbgs() << "\n");
|
|
|
|
result = ForallRewriteResult{forallMappingSizes, mappingIdOps};
|
|
return DiagnosedSilenceableFailure::success();
|
|
}
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
// MapForallToBlocks
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
DiagnosedSilenceableFailure mlir::transform::gpu::mapForallToBlocksImpl(
|
|
RewriterBase &rewriter, TransformOpInterface transformOp,
|
|
scf::ForallOp forallOp, SmallVectorImpl<int64_t> &gridDims,
|
|
const GpuIdBuilder &gpuIdBuilder) {
|
|
LDBG("Start mapForallToBlocksImpl");
|
|
|
|
{
|
|
// GPU-specific verifications. There is no better place to anchor
|
|
// those right now: the ForallOp is target-independent and the transform
|
|
// op does not apply to individual ForallOp.
|
|
DiagnosedSilenceableFailure diag =
|
|
verifyGpuMapping<BlockMappingKind>(transformOp, forallOp);
|
|
if (!diag.succeeded())
|
|
return diag;
|
|
}
|
|
|
|
Location loc = forallOp.getLoc();
|
|
Block *parentBlock = forallOp->getBlock();
|
|
Value zero;
|
|
{
|
|
// Create an early zero index value for replacements and immediately reset
|
|
// the insertion point.
|
|
OpBuilder::InsertionGuard guard(rewriter);
|
|
rewriter.setInsertionPointToStart(parentBlock);
|
|
zero = rewriter.create<arith::ConstantIndexOp>(loc, 0);
|
|
}
|
|
|
|
ForallRewriteResult rewriteResult;
|
|
DiagnosedSilenceableFailure diag = rewriteOneForallCommonImpl(
|
|
rewriter, transformOp, forallOp,
|
|
/*availableMappingSizes=*/gridDims, rewriteResult, gpuIdBuilder);
|
|
|
|
// Return if anything goes wrong, use silenceable failure as a match
|
|
// failure.
|
|
if (!diag.succeeded())
|
|
return diag;
|
|
|
|
// If gridDims was not provided already, set it from the return.
|
|
if (gridDims.empty()) {
|
|
gridDims = rewriteResult.mappingSizes;
|
|
while (gridDims.size() < 3)
|
|
gridDims.push_back(1);
|
|
}
|
|
assert(gridDims.size() == 3 && "Need 3-D gridDims");
|
|
|
|
// Replace ids of dimensions known to be 1 by 0 to simplify the IR.
|
|
// Here, the result of mapping determines the available mapping sizes.
|
|
replaceUnitMappingIdsHelper<BlockDimOp>(rewriter, loc, parentBlock, zero,
|
|
rewriteResult.mappingSizes);
|
|
|
|
return DiagnosedSilenceableFailure::success();
|
|
}
|
|
|
|
DiagnosedSilenceableFailure
|
|
mlir::transform::gpu::findTopLevelForallOp(Operation *target,
|
|
scf::ForallOp &topLevelForallOp,
|
|
TransformOpInterface transformOp) {
|
|
auto walkResult = target->walk([&](scf::ForallOp forallOp) {
|
|
if (forallOp->getParentOfType<scf::ForallOp>())
|
|
return WalkResult::advance();
|
|
if (topLevelForallOp)
|
|
// TODO: Handle multiple forall if they are independent.
|
|
return WalkResult::interrupt();
|
|
topLevelForallOp = forallOp;
|
|
return WalkResult::advance();
|
|
});
|
|
|
|
if (walkResult.wasInterrupted() || !topLevelForallOp)
|
|
return transformOp.emitSilenceableError()
|
|
<< "could not find a unique topLevel scf.forall";
|
|
return DiagnosedSilenceableFailure::success();
|
|
}
|
|
|
|
DiagnosedSilenceableFailure transform::MapForallToBlocks::applyToOne(
|
|
transform::TransformRewriter &rewriter, Operation *target,
|
|
ApplyToEachResultList &results, transform::TransformState &state) {
|
|
LaunchOp gpuLaunch = dyn_cast<LaunchOp>(target);
|
|
auto transformOp = cast<TransformOpInterface>(getOperation());
|
|
|
|
if (!getGenerateGpuLaunch() && !gpuLaunch) {
|
|
DiagnosedSilenceableFailure diag =
|
|
emitSilenceableError()
|
|
<< "Given target is not gpu.launch, set `generate_gpu_launch` "
|
|
"attribute";
|
|
diag.attachNote(target->getLoc()) << "when applied to this payload op";
|
|
return diag;
|
|
}
|
|
|
|
scf::ForallOp topLevelForallOp;
|
|
DiagnosedSilenceableFailure diag = mlir::transform::gpu::findTopLevelForallOp(
|
|
target, topLevelForallOp, transformOp);
|
|
if (!diag.succeeded()) {
|
|
diag.attachNote(target->getLoc()) << "when applied to this payload op";
|
|
return diag;
|
|
}
|
|
assert(topLevelForallOp && "expect an scf.forall");
|
|
|
|
SmallVector<int64_t> gridDims{getGridDims()};
|
|
if (!getGenerateGpuLaunch() && gridDims.size() != 3)
|
|
return transformOp.emitDefiniteFailure("transform require size-3 mapping");
|
|
|
|
OpBuilder::InsertionGuard guard(rewriter);
|
|
rewriter.setInsertionPoint(topLevelForallOp);
|
|
|
|
// Generate gpu launch here and move the forall inside
|
|
if (getGenerateGpuLaunch()) {
|
|
DiagnosedSilenceableFailure diag =
|
|
createGpuLaunch(rewriter, target->getLoc(), transformOp, gpuLaunch);
|
|
if (!diag.succeeded())
|
|
return diag;
|
|
|
|
rewriter.setInsertionPointToStart(&gpuLaunch.getBody().front());
|
|
Operation *newForallOp = rewriter.clone(*topLevelForallOp);
|
|
rewriter.eraseOp(topLevelForallOp);
|
|
topLevelForallOp = cast<scf::ForallOp>(newForallOp);
|
|
}
|
|
|
|
// The BlockIdBuilder adapts to whatever is thrown at it.
|
|
bool useLinearMapping = false;
|
|
if (topLevelForallOp.getMapping()) {
|
|
auto mappingAttr = cast<DeviceMappingAttrInterface>(
|
|
topLevelForallOp.getMapping()->getValue().front());
|
|
useLinearMapping = mappingAttr.isLinearMapping();
|
|
}
|
|
GpuBlockIdBuilder gpuBlockIdBuilder(getContext(), useLinearMapping);
|
|
|
|
diag = mlir::transform::gpu::mapForallToBlocksImpl(
|
|
rewriter, transformOp, topLevelForallOp, gridDims, gpuBlockIdBuilder);
|
|
if (!diag.succeeded())
|
|
return diag;
|
|
|
|
// Set the GPU launch configuration for the grid dims late, this is
|
|
// subject to IR inspection.
|
|
diag = alterGpuLaunch(rewriter, gpuLaunch,
|
|
cast<TransformOpInterface>(getOperation()), gridDims[0],
|
|
gridDims[1], gridDims[2]);
|
|
|
|
results.push_back(gpuLaunch);
|
|
return diag;
|
|
}
|
|
|
|
LogicalResult transform::MapForallToBlocks::verify() {
|
|
if (!getGridDims().empty() && getGridDims().size() != 3) {
|
|
return emitOpError() << "transform requires empty or size-3 grid_dims";
|
|
}
|
|
return success();
|
|
}
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
// MapNestedForallToThreads
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
static DiagnosedSilenceableFailure checkMappingSpec(
|
|
std::optional<TransformOpInterface> transformOp, scf::ForallOp forallOp,
|
|
ArrayRef<int64_t> numParallelIterations, ArrayRef<int64_t> blockOrGridSizes,
|
|
int factor, bool useLinearMapping = false) {
|
|
if (!useLinearMapping && blockOrGridSizes.front() % factor != 0) {
|
|
auto diag = definiteFailureHelper(
|
|
transformOp, forallOp,
|
|
Twine("3-D mapping: size of threadIdx.x must be a multiple of ") +
|
|
std::to_string(factor));
|
|
return diag;
|
|
}
|
|
if (computeProduct(numParallelIterations) * factor >
|
|
computeProduct(blockOrGridSizes)) {
|
|
auto diag = definiteFailureHelper(
|
|
transformOp, forallOp,
|
|
Twine("the number of required parallel resources (blocks or "
|
|
"threads) ") +
|
|
std::to_string(computeProduct(numParallelIterations) * factor) +
|
|
std::string(" overflows the number of available resources ") +
|
|
std::to_string(computeProduct(blockOrGridSizes)));
|
|
return diag;
|
|
}
|
|
return DiagnosedSilenceableFailure::success();
|
|
}
|
|
|
|
static DiagnosedSilenceableFailure
|
|
getThreadIdBuilder(std::optional<TransformOpInterface> transformOp,
|
|
scf::ForallOp forallOp, ArrayRef<int64_t> blockSizes,
|
|
int64_t warpSize, GpuIdBuilder &gpuIdBuilder) {
|
|
auto mappingAttr = cast<DeviceMappingAttrInterface>(
|
|
forallOp.getMapping()->getValue().front());
|
|
bool useLinearMapping = mappingAttr.isLinearMapping();
|
|
|
|
// Sanity checks that may result in runtime verification errors.
|
|
auto numParallelIterations =
|
|
getConstantIntValues((forallOp.getMixedUpperBound()));
|
|
if (!forallOp.isNormalized() || !numParallelIterations.has_value()) {
|
|
return definiteFailureHelper(
|
|
transformOp, forallOp,
|
|
"requires statically sized, normalized forall op");
|
|
}
|
|
int64_t factor = 1;
|
|
if (isa<GPUWarpgroupMappingAttr>(mappingAttr)) {
|
|
factor = GpuWarpgroupIdBuilder::kNumWarpsPerGroup * warpSize;
|
|
} else if (isa<GPUWarpMappingAttr>(mappingAttr)) {
|
|
factor = warpSize;
|
|
}
|
|
DiagnosedSilenceableFailure diag =
|
|
checkMappingSpec(transformOp, forallOp, numParallelIterations.value(),
|
|
blockSizes, factor, useLinearMapping);
|
|
if (!diag.succeeded())
|
|
return diag;
|
|
|
|
// Start mapping.
|
|
MLIRContext *ctx = forallOp.getContext();
|
|
gpuIdBuilder =
|
|
TypeSwitch<DeviceMappingAttrInterface, GpuIdBuilder>(mappingAttr)
|
|
.Case([&](GPUWarpgroupMappingAttr) {
|
|
return GpuWarpgroupIdBuilder(ctx, warpSize, useLinearMapping);
|
|
})
|
|
.Case([&](GPUWarpMappingAttr) {
|
|
return GpuWarpIdBuilder(ctx, warpSize, useLinearMapping);
|
|
})
|
|
.Case([&](GPUThreadMappingAttr) {
|
|
return GpuThreadIdBuilder(ctx, useLinearMapping);
|
|
})
|
|
.Default([&](DeviceMappingAttrInterface) -> GpuIdBuilder {
|
|
llvm_unreachable("unknown mapping attribute");
|
|
});
|
|
return DiagnosedSilenceableFailure::success();
|
|
}
|
|
|
|
DiagnosedSilenceableFailure mlir::transform::gpu::mapOneForallToThreadsImpl(
|
|
RewriterBase &rewriter, std::optional<TransformOpInterface> transformOp,
|
|
scf::ForallOp forallOp, ArrayRef<int64_t> blockSizes, int64_t warpSize,
|
|
bool syncAfterDistribute) {
|
|
|
|
{
|
|
// GPU-specific verifications. There is no better place to anchor
|
|
// those right now: the ForallOp is target-independent and the transform
|
|
// op does not apply to individual ForallOp.
|
|
DiagnosedSilenceableFailure diag =
|
|
verifyGpuMapping<ThreadMappingKind>(transformOp, forallOp);
|
|
if (!diag.succeeded())
|
|
return diag;
|
|
}
|
|
|
|
GpuIdBuilder gpuIdBuilder;
|
|
{
|
|
// Try to construct the id builder, if it fails, return.
|
|
DiagnosedSilenceableFailure diag = getThreadIdBuilder(
|
|
transformOp, forallOp, blockSizes, warpSize, gpuIdBuilder);
|
|
if (!diag.succeeded())
|
|
return diag;
|
|
}
|
|
|
|
Location loc = forallOp.getLoc();
|
|
OpBuilder::InsertionGuard g(rewriter);
|
|
// Insert after to allow for syncthreads after `forall` is erased.
|
|
rewriter.setInsertionPointAfter(forallOp);
|
|
ForallRewriteResult rewriteResult;
|
|
DiagnosedSilenceableFailure diag = rewriteOneForallCommonImpl(
|
|
rewriter, transformOp, forallOp, blockSizes, rewriteResult, gpuIdBuilder);
|
|
if (!diag.succeeded())
|
|
return diag;
|
|
// Add a syncthreads if needed. TODO: warpsync
|
|
if (syncAfterDistribute)
|
|
rewriter.create<BarrierOp>(loc);
|
|
|
|
return DiagnosedSilenceableFailure::success();
|
|
}
|
|
|
|
DiagnosedSilenceableFailure mlir::transform::gpu::mapNestedForallToThreadsImpl(
|
|
RewriterBase &rewriter, std::optional<TransformOpInterface> transformOp,
|
|
Operation *target, ArrayRef<int64_t> blockDims, int64_t warpSize,
|
|
bool syncAfterDistribute) {
|
|
LDBG("Start mapNestedForallToThreadsImpl");
|
|
if (blockDims.size() != 3) {
|
|
return definiteFailureHelper(transformOp, target,
|
|
"requires size-3 thread mapping");
|
|
}
|
|
|
|
// Create an early zero index value for replacements.
|
|
Location loc = target->getLoc();
|
|
Value zero = rewriter.create<arith::ConstantIndexOp>(loc, 0);
|
|
DiagnosedSilenceableFailure diag = DiagnosedSilenceableFailure::success();
|
|
WalkResult walkResult = target->walk([&](scf::ForallOp forallOp) {
|
|
diag = mlir::transform::gpu::mapOneForallToThreadsImpl(
|
|
rewriter, transformOp, forallOp, blockDims, warpSize,
|
|
syncAfterDistribute);
|
|
if (diag.isDefiniteFailure())
|
|
return WalkResult::interrupt();
|
|
if (diag.succeeded())
|
|
return WalkResult::skip();
|
|
return WalkResult::advance();
|
|
});
|
|
if (walkResult.wasInterrupted())
|
|
return diag;
|
|
|
|
// Replace ids of dimensions known to be 1 by 0 to simplify the IR.
|
|
// Here, the result of mapping determines the available mapping sizes.
|
|
replaceUnitMappingIdsHelper<ThreadIdOp>(rewriter, loc, target, zero,
|
|
blockDims);
|
|
|
|
return DiagnosedSilenceableFailure::success();
|
|
}
|
|
|
|
DiagnosedSilenceableFailure transform::MapNestedForallToThreads::applyToOne(
|
|
transform::TransformRewriter &rewriter, Operation *target,
|
|
ApplyToEachResultList &results, TransformState &state) {
|
|
LaunchOp gpuLaunch = dyn_cast<LaunchOp>(target);
|
|
auto transformOp = cast<TransformOpInterface>(getOperation());
|
|
|
|
// Basic high-level verifications.
|
|
if (!gpuLaunch)
|
|
return emitSilenceableError() << "Given target is not a gpu.launch";
|
|
|
|
// Mapping to block ids.
|
|
SmallVector<int64_t> blockDims{getBlockDims()};
|
|
DiagnosedSilenceableFailure diag =
|
|
checkGpuLimits(transformOp, std::nullopt, std::nullopt, std::nullopt,
|
|
blockDims[0], blockDims[1], blockDims[2]);
|
|
if (diag.isSilenceableFailure()) {
|
|
diag.attachNote(getLoc()) << getBlockDimsAttrName() << " is too large";
|
|
return diag;
|
|
}
|
|
|
|
// Set the GPU launch configuration for the block dims early, this is not
|
|
// subject to IR inspection.
|
|
diag = alterGpuLaunch(rewriter, gpuLaunch, transformOp, std::nullopt,
|
|
std::nullopt, std::nullopt, blockDims[0], blockDims[1],
|
|
blockDims[2]);
|
|
|
|
rewriter.setInsertionPointToStart(&gpuLaunch.getBody().front());
|
|
diag =
|
|
mapNestedForallToThreadsImpl(rewriter, transformOp, gpuLaunch, blockDims,
|
|
getWarpSize(), getSyncAfterDistribute());
|
|
|
|
results.push_back(gpuLaunch.getOperation());
|
|
return diag;
|
|
}
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
// Transform op registration
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
namespace {
|
|
/// Registers new ops and declares PDL as dependent dialect since the
|
|
/// additional ops are using PDL types for operands and results.
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class GPUTransformDialectExtension
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: public transform::TransformDialectExtension<
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GPUTransformDialectExtension> {
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public:
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MLIR_DEFINE_EXPLICIT_INTERNAL_INLINE_TYPE_ID(GPUTransformDialectExtension)
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GPUTransformDialectExtension() {
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declareGeneratedDialect<scf::SCFDialect>();
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declareGeneratedDialect<arith::ArithDialect>();
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declareGeneratedDialect<GPUDialect>();
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registerTransformOps<
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#define GET_OP_LIST
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#include "mlir/Dialect/GPU/TransformOps/GPUTransformOps.cpp.inc"
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|
>();
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}
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};
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} // namespace
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#define GET_OP_CLASSES
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#include "mlir/Dialect/GPU/TransformOps/GPUTransformOps.cpp.inc"
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|
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void mlir::gpu::registerTransformDialectExtension(DialectRegistry ®istry) {
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registry.addExtensions<GPUTransformDialectExtension>();
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}
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